Design and Implementation of a delay and area efficient 32x32bit Vedic Multiplier using Brent Kung Adder

Vedic Multiplier ◽

2014 International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE) ◽

Design and implementation of area efficient, low power AMBA-APB Bridge for SoC

10.1109/icgccee.2014.6922239 ◽

2014 ◽

Author(s):

Abhijeet Paunikar ◽

Rohan Gavankar ◽

Nachiket Umarikar ◽

K. Sivasankaran

Keyword(s):

Low Power ◽

Design and implementation of area efficient EAIC modulo adder

Materials Today Proceedings ◽

10.1016/j.matpr.2020.06.172 ◽

2020 ◽

Vol 33 ◽

pp. 3751-3756

Author(s):

Thiruvenkadam Krishnan ◽

S. Saravanan ◽

Parthibaraj Anguraj ◽

Anjali S. Pillai

Keyword(s):

An efficient design and implementation of Vedic multiplier in quantum-dot cellular automata

Telecommunication Systems ◽

10.1007/s11235-020-00669-7 ◽

2020 ◽

Vol 74 (4) ◽

pp. 487-496

Author(s):

B. Naresh Kumar Reddy ◽

B. Veena Vani ◽

G. Bhavya Lahari

Keyword(s):

Cellular Automata ◽

Quantum Dot ◽

Efficient Design ◽

Quantum Dot Cellular Automata ◽

Vedic Multiplier

Design and Implementation of Low-Power, Area-Efficient Fir Filter using Different Distributed Arithmetic Techniques

Indian Journal of Science and Technology ◽

10.17485/ijst/2015/v8i21/79128 ◽

2015 ◽

Vol 8 (21) ◽

Author(s):

Pilli Ramesh ◽

P. Augusta Sophy Beulet

Keyword(s):

Low Power ◽

Fir Filter ◽

Distributed Arithmetic ◽

International Journal of Advanced Research in Electrical Electronics and Instrumentation Engineering ◽

Low Power Area-Efficient Adiabatic Vedic Multiplier

10.15662/ijareeie.2014.0308018 ◽

2014 ◽

Vol 03 (08) ◽

pp. 11027-11032

Author(s):

K. Narendra ◽

Sagara Pandu

Keyword(s):

Low Power ◽

Vedic Multiplier ◽

2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT) ◽

Design and Implementation of Sixteen-bit Low Power and Area Efficient Dadda Multiplier

10.1109/rteict46194.2019.9016834 ◽

2019 ◽

Cited By ~ 1

Author(s):

V Manu ◽

A M Vijaya Prakash ◽

Mohan U Chandra

Keyword(s):

Low Power ◽

2018 Fourth International Conference on Computing Communication Control and Automation (ICCUBEA) ◽

Design and Implementation of 2Bit Vedic Multiplier at 16nm Using PTL Logic

10.1109/iccubea.2018.8697753 ◽

2018 ◽

Author(s):

Kshitij Sharma ◽

Anubhav Garg ◽

Deepak Agrawal ◽

Anu Mehra ◽

Smita Singhal

Keyword(s):

Vedic Multiplier

Design and Implementation of High Speed and Area Efficient MAC Unit

International Journal of MC Square Scientific Research ◽

10.20894/ijmsr.117.009.001.014 ◽

2017 ◽

Vol 9 (1) ◽

pp. 117-129

Author(s):

M. Nivedha ◽

◽

V. Priyadharshini ◽

Keyword(s):

High Speed ◽

Design and implementation of energy efficient vedic multiplier using FPGA

2015 International Conference on Information Processing (ICIP) ◽

10.1109/infop.2015.7489379 ◽

2015 ◽

Author(s):

Hemangi P. Patil ◽

S. D. Sawant

Keyword(s):

Energy Efficient ◽

Vedic Multiplier

Design and implementation of high performance and area efficient square architecture using Vedic Mathematics

Analog Integrated Circuits and Signal Processing ◽

10.1007/s10470-019-01496-w ◽

2019 ◽

Vol 102 (3) ◽

pp. 501-506 ◽

Cited By ~ 1

Author(s):

Beechu Naresh Kumar Reddy

Keyword(s):

High Performance ◽

Vedic Mathematics ◽