BIST for network on chip communication infrastructure based on combination of extended IEEE 1149.1 and IEEE 1500 standards

2011 ◽  
Vol 42 (5) ◽  
pp. 667-680 ◽  
Author(s):  
Reza Nourmandi-Pour ◽  
Nafiseh Mousavian ◽  
Ahmad Khadem-Zadeh
Keyword(s):  
Network On Chip ◽  
Communication Infrastructure ◽  
Ieee 1149.1 ◽  
On Chip

An IEEE 1149.1-based BIST method for at-speed testing of inter-switch links in network on chip

2010 ◽  
Vol 41 (7) ◽  
pp. 417-429 ◽  
Author(s):  
Reza Nourmandi-Pour ◽  
Ahmad Khadem-Zadeh ◽  
Amir Masoud Rahmani
Keyword(s):  
Network On Chip ◽  
Ieee 1149.1 ◽  
On Chip

Design Methodologies and Mapping Algorithms for Reconfigurable NoC-Based Systems

2010 ◽  
pp. 110-134 ◽  
Author(s):  
Vincenzo Rana ◽  
Marco D. Santambrogio ◽  
Alessandro Meroni
Keyword(s):  
Homogeneous Solution ◽  
Network On Chip ◽  
Target System ◽  
Communication Infrastructure ◽  
Mapping Algorithms ◽  
Design Methodologies ◽  
Reconfigurable System ◽  
Target Architecture ◽  
Run Time ◽  
On Chip

This chapter describes in details the different approaches and design methodologies that can be employed in order to create reconfigurable Network-on-Chip-based systems. The target architecture can be mainly defined either as a homogeneous or as a non-homogeneous grid of tiles. Furthermore, in addition to these architectures, it is also possible to identify a regular non-homogeneous solution, which is a sort of mix of the previous two. A second distinction can be done based on the reconfiguration capabilities that the target system can support. In particular, by using one of the previously introduced architectures, it is possible to develop a reconfigurable system, based on the NoC paradigm, in which the communication infrastructure, the mapping of the computational cores or both can be dynamically configured at run-time.

A generic FPGA prototype for on-chip systems with network-on-chip communication infrastructure

2014 ◽  
Vol 40 (1) ◽  
pp. 158-167 ◽  
Author(s):  
Mohammad Arjomand ◽  
Amirali Boroumand ◽  
Hamid Sarbazi-Azad
Keyword(s):  
Network On Chip ◽  
Communication Infrastructure ◽  
On Chip

Pre-allocated Path Based Low Latency Router Architecture for Network-on-chip

2014 ◽  
Vol 35 (2) ◽  
pp. 341-346
Author(s):  
Xiao-fu Zheng ◽  
Hua-xi Gu ◽  
Yin-tang Yang ◽  
Zhong-fan Huang
Keyword(s):  
Network On Chip ◽  
Low Latency ◽  
Router Architecture ◽  
On Chip
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