Design Methodologies and Mapping Algorithms for Reconfigurable NoC-Based Systems

2010 ◽  
pp. 110-134 ◽  
Author(s):  
Vincenzo Rana ◽  
Marco D. Santambrogio ◽  
Alessandro Meroni
Keyword(s):  
Homogeneous Solution ◽  
Network On Chip ◽  
Target System ◽  
Communication Infrastructure ◽  
Mapping Algorithms ◽  
Design Methodologies ◽  
Reconfigurable System ◽  
Target Architecture ◽  
Run Time ◽  
On Chip

This chapter describes in details the different approaches and design methodologies that can be employed in order to create reconfigurable Network-on-Chip-based systems. The target architecture can be mainly defined either as a homogeneous or as a non-homogeneous grid of tiles. Furthermore, in addition to these architectures, it is also possible to identify a regular non-homogeneous solution, which is a sort of mix of the previous two. A second distinction can be done based on the reconfiguration capabilities that the target system can support. In particular, by using one of the previously introduced architectures, it is possible to develop a reconfigurable system, based on the NoC paradigm, in which the communication infrastructure, the mapping of the computational cores or both can be dynamically configured at run-time.

Dynamic Reconfigurable NoCs

2010 ◽  
pp. 158-185
Author(s):  
Vincenzo Rana ◽  
Marco Domenico Santambrogio ◽  
Simone Corbetta
Keyword(s):  
Communication Protocol ◽  
Communication Infrastructure ◽  
Reconfigurable System ◽  
Physical Implementation ◽  
Target Architecture ◽  
Routing Mechanism ◽  
Layered Approach ◽  
Definition Of ◽  
Network Switches

The aim of this chapter is the definition of the main issues that arise when dealing with the design of a NoC-based reconfigurable system. In particular, after the definition of the target architecture, several factors, requirements and constraints that have to be taken into account during the design of reconfigurable NoCs will be described and analyzed. The second part of this chapter will focus on the main issues in dynamic reconfigurable NoCs design, such as the definition of a layered approach, of a packet-switched communication infrastructure, of a proper routing mechanism and of a communication protocol support. Finally, the last part of this chapter will deal with the description of the most relevant implementation details, such as the placement of the bus-macros, the design of the network switches and the physical implementation of the routing mechanism.

Dual Monitoring Communication for Self-Aware Network-on-Chip

2012 ◽  
Vol 3 (3) ◽  
pp. 72-91
Author(s):  
Liang Guang ◽  
Ethiopia Nigussie ◽  
Juha Plosila ◽  
Hannu Tenhunen
Keyword(s):  
High Speed ◽  
Data Communication ◽  
Cmos Technology ◽  
Network On Chip ◽  
Time Profile ◽  
Self Awareness ◽  
Monitoring Networks ◽  
Communication Architecture ◽  
Run Time ◽  
On Chip

Self-aware and adaptive Network-on-Chip (NoC) with dual monitoring networks is presented. Proper monitoring interface is an essential prerequisite to adaptive system reconfiguration in parallel on-chip computing. This work proposes a DMC (dual monitoring communication) architecture to support self-awareness on the NoC platform. One type of monitoring communication is integrated with data channel, in order to trace the run-time profile of data communication in high-speed on-chip networking. The other type is separate from the data communication, and is needed to report the run-time profile to the supervising monitor. Direct latency monitoring on mesochronous NoC is presented as a case study and is directly traced in the integrated communication with a novel latency monitoring table in each router. The latency information is reported by the separate monitoring communication to the supervising monitor, which reconfigures the system to adjust the latency, for instance by dynamic voltage and frequency scaling. With quantitative evaluation using synthetic traces and real applications, the effectiveness and efficiency of direct latency monitoring with DMC architecture is demonstrated. The area overhead of DMC architecture is estimated to be small in 65nm CMOS technology.

Comparison of network-on-chip mapping algorithms targeting low energy consumption

2008 ◽  
Vol 2 (6) ◽  
pp. 471 ◽  
Author(s):  
C.A.M. Marcon ◽  
E.I. Moreno ◽  
N.L.V. Calazans ◽  
F.G. Moraes
Keyword(s):  
Energy Consumption ◽  
Network On Chip ◽  
Low Energy ◽  
Mapping Algorithms ◽  
Low Energy Consumption ◽  
On Chip

scholarly journals Adaptivity Support for MPSoCs Based on Process Migration in Polyhedral Process Networks

VLSI Design ◽  
2012 ◽  
Vol 2012 ◽  
pp. 1-17 ◽  
Author(s):  
Emanuele Cannella ◽  
Onur Derin ◽  
Paolo Meloni ◽  
Giuseppe Tuveri ◽  
Todor Stefanov
Keyword(s):  
Real Life ◽  
Data Communication ◽  
Network On Chip ◽  
Process Migration ◽  
Model Of Computation ◽  
Process Networks ◽  
Time Migration ◽  
Migration Mechanism ◽  
Run Time ◽  
On Chip

System adaptivity is becoming an important feature of modern embedded multiprocessor systems. To achieve the goal of system adaptivity when executing Polyhedral Process Networks (PPNs) on a generic tiled Network-on-Chip (NoC) MPSoC platform, we propose an approach to enable the run-time migration of processes among the available platform resources. In our approach, process migration is allowed by a middleware layer which comprises two main components. The first component concerns the inter-tile data communication between processes. We develop and evaluate a number of different communication approaches which implement the semantics of the PPN model of computation on a generic NoC platform. The presented communication approaches do not depend on the mapping of processes and have been implemented on a Network-on-Chip multiprocessor platform prototyped on an FPGA. Their comparison in terms of the introduced overhead is presented in two case studies with different communication characteristics. The second middleware component allows the actual run-time migration of PPN processes. To this end, we propose and evaluate a process migration mechanism which leverages the PPN model of computation to guarantee a predictable and efficient migration procedure. The efficiency and applicability of the proposed migration mechanism is shown in a real-life case study.

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