A novel power efficient 0.64-GFlops fused 32-bit reversible floating point arithmetic unit architecture for digital signal processing applications

Digital Signal ◽

Floating Point ◽

Arithmetic Unit ◽

Power Efficient ◽

Floating-point arithmetic for digital signal processing

10.1109/icassp.1980.1170952 ◽

2005 ◽

Author(s):

W. Koral ◽

L. Schirm

Keyword(s):

Signal Processing ◽

Digital Signal ◽

Floating Point ◽

2011 Conference Record of the Forty Fifth Asilomar Conference on Signals, Systems and Computers (ASILOMAR) ◽

Energy-efficient floating-point arithmetic for digital signal processors

10.1109/acssc.2011.6190337 ◽

2011 ◽

Cited By ~ 2

Author(s):

Syed Zohaib Gilani ◽

Nam Sung Kim ◽

Michael Schulte

Keyword(s):

Energy Efficient ◽

Digital Signal ◽

Digital Signal Processors ◽

Floating Point ◽

Signal Processors ◽

2007 International Conference on Signal Processing, Communications and Networking ◽

A 1 GHz Pipelined Low Power Floating Point Arithmetic Unit with Modified Scheduling for High Speed Applications

10.1109/icscn.2007.350766 ◽

2007 ◽

Cited By ~ 3

Author(s):

K.M. Mukund ◽

Sudharsan Seshadri ◽

Janarthanan Devarajulu ◽

M. Kannan

Keyword(s):

Low Power ◽

High Speed ◽

Floating Point ◽

Arithmetic Unit ◽

A bit-serial floating-point complex multiplier-accumulator for fault-tolerant digital signal processing arrays

10.1109/icassp.1987.1169739 ◽

2005 ◽

Author(s):

P. Chau ◽

K. Chew ◽

W. Ku

Keyword(s):

Signal Processing ◽

Fault Tolerant ◽

Digital Signal ◽

Floating Point ◽

Complex Multiplier ◽

Bit Serial

Low cost floating point arithmetic unit design

Proceedings. IEEE Asia-Pacific Conference on ASIC, ◽

10.1109/apasic.2002.1031571 ◽

2003 ◽

Cited By ~ 2

Author(s):

Seungchul Kim ◽

Yongjoo Lee ◽

Wookyeong Jeong ◽

Yongsurk Lee

Keyword(s):

Low Cost ◽

Floating Point ◽

Arithmetic Unit ◽

Unit Design ◽

A high-speech 32 bit IEEE floating-point chip set for digital signal processing

10.1109/icassp.1984.1172306 ◽

2005 ◽

Author(s):

Bob Woo ◽

Lyon Lin ◽

F. Ware

Keyword(s):

Signal Processing ◽

Digital Signal ◽

Floating Point

2018 International Conference on Intelligent Transportation, Big Data & Smart City (ICITBS) ◽

The Design and Implementation of Multi-Precision Floating Point Arithmetic Unit Based on FPGA

10.1109/icitbs.2018.00154 ◽

2018 ◽

Cited By ~ 1

Author(s):

Lei Kang ◽

Cailing Wang

Keyword(s):

Floating Point ◽

Arithmetic Unit ◽

Design And Implementation ◽

A performance-optimized reconfigurable arithmetic unit for digital signal processing

International Workshop on Communication Technology 2013 ◽

10.2495/cecnet130301 ◽

2014 ◽

Author(s):

Chunyang Feng

Keyword(s):

Signal Processing ◽

Digital Signal ◽

Arithmetic Unit ◽

A Performance

Design and Analysis of Multimode Single Precision Floating Point Arithmetic Unit Using Verilog

International Journal of Scientific Research and Management ◽

10.18535/ijsrm/v5i5.08 ◽

2017 ◽

Author(s):

Sachin saraswat ◽

Keyword(s):

Floating Point ◽

Arithmetic Unit ◽

Single Precision ◽

Efficient Floating-Point Division for Digital Signal Processing Application [Tips & Tricks]

IEEE Signal Processing Magazine ◽

10.1109/msp.2018.2875977 ◽

2019 ◽

Vol 36 (1) ◽

pp. 159-163 ◽

Cited By ~ 1

Author(s):

Leonid Moroz ◽

Volodymyr Samotyy

Keyword(s):

Signal Processing ◽

Digital Signal ◽

Floating Point ◽

Processing Application ◽

Digital Signal Processing Application ◽

Signal Processing Application