Enhanced and Efficient Carry Select Adder with Minimal Delay

In today’s digital world, Arithmetic computations have been evolved as a core factor in digital signal processors, micro-controllers, and systems using arithmetic and logical operations such as adders, multipliers, image processors, and signal processors. One of the elements that play an important role in performing arithmetic calculations is an adder. Among many adders, the Carry Select Adder produces less propagation delay. However, there may be an increased delay, power consumption, and area required in the case of a normal Carry Select Adder. To overcome the mentioned drawbacks, an improved model of Carry Select Adder has been designed that uses Binary to Excess – 1 Converter. Instead of using multiple blocks of Ripple Carry Adders (RCAs), it is efficient and effective if one of the blocks is replaced with Binary to Excess – 1 Converter. As a result, we can achieve a high speed adder with minimal delay, minimal power, and reduced area.

Simulation and Analysis of different CMOS Full Adders for Delay Optimisation

Full adder circuit is one among the fundamental and necessary digital part. The full adder is be a part of microprocessors, digital signal processors etc. It's needed for the arithmetic and logical operations. Full adder design enhancements are necessary for recent advancement. The requirement of an adder cell is to provide high speed, consume low power and provide high voltage swing. This paper analyses and compares 3 adders with completely different logic designs (Conventional, transmission gate & pseudo NMOS) for transistor count, power dissipation and delay. The simulation is performed in Cadence virtuoso tool with accessible GPDK – 180nm kit. Transmission gate full adder has sheer advantage of high speed, fewer space and also it shows higher performance in terms of delay. Keywords: Delay, power dissipation, voltage, transistor sizing.

A Review on IEEE-754 Standard Floating Point Multiplier using Vedic Mathematics

The fundamental and the core of all the Digital Signal Processors (DSPs) are its multipliers and the speed of the DSPs is mainly determined by the speed of its multiplier. IEEE floating point format is a standard format used in all processing elements since Binary floating point numbers multiplication is one of the basic functions used in digital signal processing (DSP) application. In this work VHDL implementation of Floating Point Multiplier using Vedic mathematics is carried out. The Urdhva Tiryakbhyam sutra (method) was selected for implementation since it is applicable to all cases of multiplication. Multiplication of two no’s using Urdhva Tiryakbhyam sutra is performed by vertically and crosswise. The feature is any multi-bit multiplication can be reduced down to single bit multiplication and addition using this method. On account of these formulas, the carry propagation from LSB to MSB is reduces due to one step generation of partial product.

A Fresh Design of Power Effective Adapted Vedic Multiplier for Modern Digital Signal Processors

The Multiply Accumulate (MAC) unit constructed using antiquated Vedic mathematical practice and the efficiency of the vertical and transversely of Vedic approach for multiplication, which gives a distinction in genuine cycle of Multiplier itself. Vedic-Mathematics is depend on 16-Sutras, in that Urdhva-Triyakbhyam (UT) more productive one. It literally means vertical and cross wise operations. It eliminates unwanted multiplication and allows the parallel creation of partial products and addition steps. The adders are utilized to append the partial-product generated in the Vedic mathematics methodology to drops the combinational lag. MAC is an essential unit in the digital signal processors, to show the characters like speed, power as well as area. Hence, finer multiplier plans are to increase the order of the system. The Modified sum product algorithm based Vedic multiplier is one such promising solution. It has a rapid multiplication process and reaches a less calculation complexity above its traditional multiplier. Array multiplier, Baugh-Wooley multiplier, Wallace-tree multiplier and Vedic multiplier were created in the existing work. In proposed work Vedic multiplier, using modified sum product algorithm was designed. The structure design coded in verilog and parameter analysis was done in Xilinx. The parameters like delay as well as power were compare between existing and proposed. When comparing with different multiplier with our proposed work delay get reduced. Comparing with existing multiplier the proposed 4x4 Vedic multiplier have 49.12% reduction in delay. Comparing with existing multiplier the proposed Vedic 4x4 multiplier have 42.51% reduction in power.

An Efficient Design of 16 Bit MAC Unit using Vedic Mathematics

Duplicate and Accumulate (MAC) is one of the central practices utilized absolutely in signal- controlling and different applications. The multiplier is the major piece of Digital Signal Processors (DSPs). Its cutoff spins around power, LUT use, and surrender pick the presence of a DSP. In like way, there is a need to sort out the drive and give up fit multiplier. In this paper, a 16-digit MAC unit is proposed to utilize an 8-cycle Vedic multiplier and pass on a save snake. A relationship with the current 8-cycle Vedic multiplier utilizing Square-Root (SQR) Carry-select snake (CSLA) is introduced. It is isolated and a standard pack multiplier. The whole technique is done in Verilog HDL. Blend and redirections were finished utilizing Xilinx InDesign Suite 14.5. The proposed game plan accomplishes fundamental improvement in region and suspension. In like manner, an abatement in power around 9.5% is refined.