scholarly journals Area Efficient Hybrid Parallel Prefix Adders

2015 ◽  
Vol 10 ◽  
pp. 371-380 ◽  
Author(s):  
N. Poornima ◽  
V. S. Kanchana Bhaaskaran
Keyword(s):  
Parallel Prefix ◽  
Prefix Adders ◽  
Area Efficient

scholarly journals Design and Estimation of delay, power and area for Parallel prefix adders

2017 ◽  
Vol 07 (04) ◽  
pp. 01-08
Author(s):  
Avinash Shrivastava ◽  
Shefali Churhe ◽  
Hemlata Bhagat ◽  
Rajni Wamankar
Keyword(s):  
Parallel Prefix ◽  
Prefix Adders

scholarly journals A Novel Architecture for Multiplier and Accumulator unit by using Parallel Prefix Adders

IJARCCE ◽  
2019 ◽  
Vol 8 (6) ◽  
pp. 60-64
Author(s):  
Nagarajan N. R. ◽  
Muruganantham T. ◽  
Rajapriya S.
Keyword(s):  
Parallel Prefix ◽  
Prefix Adders

On the Diminished-1 Modulo 2n+1 Addition and Subtraction

2019 ◽  
Vol 29 (05) ◽  
pp. 2030005
Author(s):  
Constantinos Efstathiou ◽  
Kiamal Pekmestzi ◽  
Nikolaos Moshopoulos
Keyword(s):  
Power Consumption ◽  
Lower Power ◽  
Look Ahead ◽  
Parallel Prefix ◽  
Addition And Subtraction ◽  
Arithmetic Units ◽  
Prefix Adders

In this work, the design of the diminished-1 modulo [Formula: see text] adders, subtractors and adders/subtractors are examined. Some of the existing modulo [Formula: see text] adders, subtractors and adder/subtractors are redesigned and improved. Compared to other existing implementations, the proposed subtractor and adder/subtractors offer reduced area complexity and lower power consumption, while operating at the same speed. All the considered architectures are modified parallel-prefix adders with fast input carry processing. The totally parallel-prefix and carry look ahead implementation of the proposed arithmetic units are also discussed.

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