An Efficient High-Speed CORDIC Algorithm Using Parallel-Prefix Adders (PPA)

2019 ◽  
pp. 805-813
Author(s):  
Vutukuri Venkatesh ◽  
Balaji Yeswanth ◽  
Repala Akhil ◽  
Ravi Kumar Jatoth
Keyword(s):  
High Speed ◽  
Cordic Algorithm ◽  
Parallel Prefix ◽  
Prefix Adders

scholarly journals Design a High Speed Multiplier using Two Phase PPA

2019 ◽  
Vol 8 (11S2) ◽  
pp. 146-149
Keyword(s):  
High Speed ◽  
Two Phase ◽  
Ripple Carry Adder ◽  
Product Generation ◽  
Different Types ◽  
Effective System ◽  
Parallel Prefix ◽  
Three Stages ◽  
Prefix Adder ◽  
Prefix Adders

Basically, multiplier is an efficient superconductor logic which performs various switching operation. Here different types of adders are analysed using different methodologies. In this paper we introduced a multiplier using proposed PPA. It uses parallel prefix adders in their reduction phase and it is an effective system for faster results and optimised. The entire operation of proposed system depends upon three stages they are multiplier partial product generation, reduction stages and parallel prefix adder which is discussed in below sections. The delay gets reduced by achieving low logical depth in the system. So the Proposed system reduces the delay. From the proposed system we can observe that there is a reduction in delay and complexity. Compared to ripple carry adder and carry save adder, proposed system gives better results.

scholarly journals Implementation and Comparison of Radix-8 Booth Multiplier by using 32-bit Parallel prefix adders for High Speed Arithmetic Applications

2021 ◽  
Vol 12 (3) ◽  
pp. 5673-5683
Author(s):  
Barma Venkata RamaLakshmi Et. al.
Keyword(s):  
High Speed ◽  
High Performance ◽  
Digital Systems ◽  
High Demand ◽  
Major Drawback ◽  
Booth Multiplier ◽  
Computational Speed ◽  
Parallel Prefix ◽  
Simulation Results ◽  
Prefix Adders

This paper presents the implementation and design of  Radix-8 booth Multiplier using 32-bit parallel prefix adders. High performance processors have a high demand in the industrial market. For achieving high performance and to enhance the computational speed multiplier plays a key role in performance of digital system. But the major drawback is it consumes more power , area and delay. To enhance the performance and decrease the area consumption and delay there are many algorithms and techniques. In this paper we designed a radix-8 Booth Multiplier using two parallel prefix adders and compared them for best optimized multiplier. The number of parital products generation can be reduced by n/3 by using radix-8 in the multiplier encoding. To further reduce the additions we have used booth recoding mechanism .We have implemented the design using Kogge stone adder and Brent kung adder. We observed that by using parallel prefix adders reduces the delay further more which results in significant increase in speed of the digital systems. The simulation results are carried out on XILINX VIVADO software.

scholarly journals Design and Implementation of High Speed Area Efficient Carry Select Adder Using Spanning Tree Adder Technique

2018 ◽  
pp. 21-26
Author(s):  
Hima Bindu Vykuntam ◽  
Chennaiah M ◽  
Sudhakar K
Keyword(s):  
Spanning Tree ◽  
High Speed ◽  
Computation Time ◽  
Digital Design ◽  
Comparative Performance ◽  
Ripple Carry Adder ◽  
Parallel Prefix ◽  
Carry Select Adder ◽  
Prefix Adder ◽  
Prefix Adders

In this paper, we propose Carry Select Adder (CSLA) architecture with parallel prefix adder. Instead of using 4-bit Brent Kung Adder (BKA), another parallel prefix adder i.e., 4-bit spanning Tree (ST) adder is used to design CSA. Because Adders are key element in digital design, which are not only performing addition operation, but also many other function such as subtraction, multiplication and division. A Ripple Carry Adder (RCA) gives the most complicated design as-well-as longer computation time so that we may gone for parallel prefix adders. This time critical application we use Spanning tree parallel prefix adder to drive fast results but they lead to increase in area. Proposed Carry Select Adder understands between RCA and BKA in term of area and delay. Delay of Existing adders is larger therefore we have replaced those with Brent Spanning Tree parallel prefix adder which gives fast result. This paper describes comparative performance of 4-bit RCA and 4-Bit BK parallel prefix adders with Our Proposed Spanning Tree adder based carry select adder designed using Xilinx ISE tool.

scholarly journals Low Power High Speed Arithmetic Circuits

2019 ◽  
Vol 8 (2) ◽  
pp. 807-813 ◽  
Keyword(s):  
Low Power ◽  
System Design ◽  
High Speed ◽  
Arithmetic Circuits ◽  
Booth Multiplier ◽  
Vedic Multiplier ◽  
Vlsi System ◽  
Parallel Prefix ◽  
Prefix Adders ◽  
Vlsi System Design

In the Design of arithmetic circuits reducing area, high speed and power are the major areas in VLSI system design. In this paper parallel prefix adders like Kogge-stone adder, Breunt-Kung adder, Ladner-Fischer adder is designed .Radix-4 Booth multiplier is designed by using Kogge-Stone adder. 16 bit Vedic multiplier is done by using Urdhwa Triyambaka sutra .8bit Vedic division is implemented by using Crumbs method so as to reduce the area, LUT tables and increase the speed as well as to reduce the Power dissipiation. The design is synthesized using Xilinx ISE 14.1 design suite.

scholarly journals Design of High-Speed Adders for Efficient Digital Design Blocks

2012 ◽  
Vol 2012 ◽  
pp. 1-9 ◽  
Author(s):  
Deepa Yagain ◽  
Vijaya Krishna A ◽  
Akansha Baliga
Keyword(s):  
Digital Signal Processor ◽  
High Speed ◽  
Digital Signal ◽  
Digital Design ◽  
Data Path ◽  
Lattice Filter ◽  
Cmos Design ◽  
Addition Problem ◽  
Parallel Prefix ◽  
Prefix Adders

The core of every microprocessor and digital signal processor is its data path. The heart of data-path and addressing units in turn are arithmetic units which include adders. Parallel-prefix adders offer a highly efficient solution to the binary addition problem and are well suited for VLSI implementations. This paper involves the design and comparison of high-speed, parallel-prefix adders such as Kogge-Stone, Brent-Kung, Sklansky, and Kogge-Stone Ling adders. It is found that Kogge-Stone Ling adder performs much efficiently when compared to the other adders. Here, Kogge-Stone Ling adders and ripple adders are incorporated as a part of a lattice filter in order to prove their functionalities. It is seen that the operating frequency of lattice filter increases if parallel prefix Kogge-Stone Ling adder is used instead of ripple adders since the combinational delay of Kogge-Stone Ling adder is less. Further, design and comparison of different tree adder structures are performed using both CMOS logic and transmission gate logic. Using these adders, unsigned and signed comparators are designed as an application example and compared with their performance parameters such as area, delay, and power consumed. The design and simulations are done using 65 nm CMOS design library.

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