On the Diminished-1 Modulo 2n+1 Addition and Subtraction

2019 ◽  
Vol 29 (05) ◽  
pp. 2030005
Author(s):  
Constantinos Efstathiou ◽  
Kiamal Pekmestzi ◽  
Nikolaos Moshopoulos
Keyword(s):  
Power Consumption ◽  
Lower Power ◽  
Look Ahead ◽  
Parallel Prefix ◽  
Addition And Subtraction ◽  
Arithmetic Units ◽  
Prefix Adders

In this work, the design of the diminished-1 modulo [Formula: see text] adders, subtractors and adders/subtractors are examined. Some of the existing modulo [Formula: see text] adders, subtractors and adder/subtractors are redesigned and improved. Compared to other existing implementations, the proposed subtractor and adder/subtractors offer reduced area complexity and lower power consumption, while operating at the same speed. All the considered architectures are modified parallel-prefix adders with fast input carry processing. The totally parallel-prefix and carry look ahead implementation of the proposed arithmetic units are also discussed.

scholarly journals Analysis of CMOS Logic and Transmission Gate for 64 Bit Parallel Prefix Adders

2018 ◽  
Vol 7 (2) ◽  
pp. 115
Author(s):  
Nehru.K K ◽  
Nagarjuna T ◽  
Somanaidu U
Keyword(s):  
High Performance ◽  
Digital Signal ◽  
Digital Signal Processors ◽  
Transmission Technique ◽  
Look Ahead ◽  
Parallel Prefix ◽  
Prefix Adder ◽  
Signal Processors ◽  
Prefix Adders ◽  
Better Than

<span>Parallel prefix adder network is a type of carry look ahead adder structure. It is widely considered as the fastest adder and used for high performance arithmetic circuits in the digital signal processors. In this article, an introduction to the design of 64 bit parallel prefix adder using transmission technique which acquires least no of nodes<strong> </strong>with the lowest transistor<strong> </strong>count and low power consumption is presented. The 64 bit parallel prefix adder is designed and comparison is made between other previously parallel prefix adders. The result shows that the proposed 64 bit parallel prefix adder is slightly better than existing parallel prefix adders and it considerably increases the computation speed.The spice tool is used for analysis with different supply voltages.</span>

scholarly journals Architecture of 2X2 FIR Filter using Vedic Multiplier and Brent-Kung Adder

2020 ◽  
Vol 9 (5) ◽  
pp. 1638-1642
Keyword(s):  
Power Consumption ◽  
Fir Filter ◽  
Booth Multiplier ◽  
Look Ahead ◽  
Vedic Multiplier ◽  
Ripple Carry Adder ◽  
Parallel Prefix ◽  
The Common ◽  
The Look ◽  
Prefix Adder

This paper proposed, a 2X2 FIR filter which is based on the Brent-Kung adder and Vedic multiplier. A 2X2 FIR filter has been designed using Brent-Kung-Adder (BKA) and filter coefficient. Verilog platform and Xilinx 14.5 software. The BrentKung adder is much faster than the look ahead carry adder (LACD), carry select adder and ripple carry adder (RCA) and it is a parallel prefix adder. Lowarea and the power consumption in Brent-kung adder is also less as compared to various adders. Multiplication of a number using the Vedic multiplier is arithmetic key operation to be performed with low power consumption of and increase the speed in the consequence applications. Proposed design utilize the common multiplication in cross multiply to compensate the problem of delay which is occurring in the Booth Multiplier and Array Multiplier and etc. Brent-kung adder used to decrease the delay which was occur in the multiplier and significantly reduce the quantity of logic elements such as gates, signals etc.

scholarly journals Study of performance of Adiabatic Carry Look Ahead Adder Using Dynamic CMOS Logic

2012 ◽  
pp. 140-142
Author(s):  
G.S. Tripathi ◽  
Shiv Prakash Arya ◽  
Rajan Mishra
Keyword(s):  
Power Consumption ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Performance Comparison ◽  
Lower Power ◽  
Look Ahead ◽  
Result Show ◽  
Pass Transistor

Performance of adiabatic carry look ahead adder using dynamic CMOS are studied and compared with Adiabatic carry look ahead adder using Pass Transistor. adiabatic carry look ahead adder using pass transistor has higher delay and lower power consumption while adiabatic carry look ahead adder using dynamic cmos logic has lower power dissipation and higher speed. adiabatic carry look ahead adder using dynamic cmos are design using 180 nm cmos technology and compared power dissipation and delay with respect to supply voltage and frequency. simulation result show that power dissipation of carry look ahead adder using dynamic cmos has higher performance comparison adiabatic CLA using pass transistor. simulation result show that adiabatic CLA using dynamic cmos reduce the power consumption 45% and delay reduce to 70% comparison to adiabatic CLA using pass transistor.

A LOW-POWER AND HIGH-SPEED D FLIP-FLOP USING A SINGLE LATCH

2002 ◽  
Vol 11 (01) ◽  
pp. 51-55
Author(s):  
ROBERT C. CHANG ◽  
L.-C. HSU ◽  
M.-C. SUN
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Operating Frequency ◽  
Flip Flop ◽  
Lower Power ◽  
Simulation Results ◽  
Hspice Simulation

A novel low-power and high-speed D flip-flop is presented in this letter. The flip-flop consists of a single low-power latch, which is controlled by a positive narrow pulse. Hence, fewer transistors are used and lower power consumption is achieved. HSPICE simulation results show that power dissipation of the proposed D flip-flop has been reduced up to 76%. The operating frequency of the flip-flop is also greatly increased.

scholarly journals Single-Electron Memories

VLSI Design ◽  
1998 ◽  
Vol 8 (1-4) ◽  
pp. 219-223 ◽  
Author(s):  
Christoph Wasshuber ◽  
Hans Kosina ◽  
Siegfried Selberherr
Keyword(s):  
Power Consumption ◽  
Room Temperature ◽  
State Of The Art ◽  
Memory Cell ◽  
Single Electron ◽  
Lower Power ◽  
Memory Chip ◽  
Single Electronics ◽  
Background Charge ◽  
Random Background

One of the most promising applications of single-electronics is a single-electron memory chip. Such a chip would have orders of magnitude lower power consumption compared to state-of-the-art dynamic memories, and would allow integration densities beyond the tera bit chip.We studied various single-electron memory designs. Additionally we are proposing a new memory cell which we call the T-memory cell. This cell can be manufactured with state-of-the-art lithography, it operates at room temperature and shows a strong resistance against random background charge.

scholarly journals Design and Estimation of delay, power and area for Parallel prefix adders

2017 ◽  
Vol 07 (04) ◽  
pp. 01-08
Author(s):  
Avinash Shrivastava ◽  
Shefali Churhe ◽  
Hemlata Bhagat ◽  
Rajni Wamankar
Keyword(s):  
Parallel Prefix ◽  
Prefix Adders

scholarly journals A Novel Architecture for Multiplier and Accumulator unit by using Parallel Prefix Adders

IJARCCE ◽  
2019 ◽  
Vol 8 (6) ◽  
pp. 60-64
Author(s):  
Nagarajan N. R. ◽  
Muruganantham T. ◽  
Rajapriya S.
Keyword(s):  
Parallel Prefix ◽  
Prefix Adders
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