scholarly journals Shortest Path Routing Algorithm for Hierarchical Interconnection Network-on-Chip

2015 ◽  
Vol 56 ◽  
pp. 409-414 ◽  
Author(s):  
Omair Inam ◽  
Sharifa Al Khanjari ◽  
Wim Vanderbauwhede
Keyword(s):  
Shortest Path ◽  
Interconnection Network ◽  
Routing Algorithm ◽  
Network On Chip ◽  
Shortest Path Routing ◽  
On Chip

OPTIMUM CONGESTED ROUTING STRATEGY ON TWISTED CUBES

2000 ◽  
Vol 01 (02) ◽  
pp. 115-134 ◽  
Author(s):  
TSENG-KUEI LI ◽  
JIMMY J. M. TAN ◽  
LIH-HSING HSU ◽  
TING-YI SUNG
Keyword(s):  
Shortest Path ◽  
Time Complexity ◽  
Interconnection Network ◽  
Routing Algorithm ◽  
Optimum Time ◽  
Shortest Path Routing ◽  
Routing Strategy ◽  
Bisection Width ◽  
Twisted Cube ◽  
Twisted Cubes

Given a shortest path routing algorithm of an interconnection network, the edge congestion is one of the important factors to evaluate the performance of this algorithm. In this paper, we consider the twisted cube, a variation of the hypercube with some better properties, and review the existing shortest path routing algorithm8. We find that its edge congestion under the routing algorithm is high. Then, we propose a new shortest path routing algorithm and show that our algorithm has optimum time complexity O(n) and optimum edge congestion 2n. Moreover, we calculate the bisection width of the twisted cube of dimension n.

scholarly journals Design and implementation of secured agent based NoC using shortest path routing algorithm

2019 ◽  
Vol 9 (2) ◽  
pp. 950
Author(s):  
Kendaganna Swamy S ◽  
Anand Jatti ◽  
Uma B. V.
Keyword(s):  
Shortest Path ◽  
High Performance ◽  
Fault Tolerant ◽  
Routing Algorithm ◽  
System On Chip ◽  
Multiprocessor System ◽  
Shortest Path Routing ◽  
Agent Based ◽  
On Chip ◽  
Fault Information

Network on chip (NoC) is a scalable interconnection architecture for every increasing communication demand between many processing cores in system on chip design. Reliability aspects are becoming an important issue in fault tolerant architecture. Hence there is a demand for fault tolerant Agent architecture with suitable routing algorithm which plays a vital role in order to enhance the NoC performance. The proposed fault tolerant Agent based NoC method is used to enhance the reliability and performance of the Multiprocessor System on Chip (MPSoC) design against faulty links and nodes. These agents are placed in hierarchical manner to collect, process, classify and distribute different fault information related to the faulty links and nodes of the network. This fault information is used for further packet routing in the network with the help of shortest path routing algorithm. In addition to this the agent will provide the security for the node by setting firewall, which then decides whether the packet has to be processed or not. This intern provides high performance, low latency NoC by avoiding deadlock and live lock with low area overhead.

scholarly journals Load-balanced routing algorithm for Network-on-Chip employing fair arbiter

2021 ◽  
Vol 1871 (1) ◽  
pp. 012117
Author(s):  
Lu Liu ◽  
Yanfei Yang ◽  
Qianqian Lei ◽  
Huhu Wang ◽  
Song Lixun
Keyword(s):  
Routing Algorithm ◽  
Network On Chip ◽  
On Chip ◽  
Load Balanced

A Recursive Shortest Path Routing Algorithm With Application for Wireless Sensor Network Localization

2016 ◽  
Vol 16 (11) ◽  
pp. 4631-4637 ◽  
Author(s):  
Juan Cota-Ruiz ◽  
Pablo Rivas-Perea ◽  
Ernesto Sifuentes ◽  
Rafael Gonzalez-Landaeta
Keyword(s):  
Wireless Sensor Network ◽  
Sensor Network ◽  
Shortest Path ◽  
Routing Algorithm ◽  
Wireless Sensor ◽  
Sensor Network Localization ◽  
Shortest Path Routing ◽  
Network Localization

A Novel Adaptive Routing Algorithm for Network-On-Chip

2011 ◽  
Vol 474-476 ◽  
pp. 413-416
Author(s):  
Jia Jia ◽  
Duan Zhou ◽  
Jian Xian Zhang
Keyword(s):  
Routing Algorithm ◽  
Adaptive Routing ◽  
Network On Chip ◽  
Experimental Results ◽  
Average Latency ◽  
On Chip

In this paper, we propose a novel adaptive routing algorithm to solve the communication congestion problem for Network-on-Chip (NoC). The strategy competing for output ports in both X and Y directions is employed to utilize the output ports of the router sufficiently, and to reduce the transmission latency and improve the throughput. Experimental results show that the proposed algorithm is very effective in relieving the communication congestion, and a reduction in average latency by 45.7% and an improvement in throughput by 44.4% are achieved compared with the deterministic XY routing algorithm and the simple XY adaptive routing algorithm.

Design of Router Supporting Multiply Routing Algorithm for NoC

2014 ◽  
Vol 981 ◽  
pp. 431-434
Author(s):  
Zhan Peng Jiang ◽  
Rui Xu ◽  
Chang Chun Dong ◽  
Lin Hai Cui
Keyword(s):  
Complex System ◽  
High Performance ◽  
Routing Algorithm ◽  
Network On Chip ◽  
System On Chip ◽  
Low Latency ◽  
Deterministic Routing ◽  
Key Features ◽  
Design Challenge ◽  
On Chip

Network on Chip(NoC)，a new proposed solution to solve global communication problem in complex System on Chip (SoC) design，has absorbed more and more researchers to do research in this area. Due to some distinct characteristics, NoC is different from both traditional off-chip network and traditional on-chip bus，and is facing with the huge design challenge. NoC router design is one of the most important issues in NoC system. The paper present a high-performance, low-latency two-stage pipelined router architecture suitable for NoC designs and providing a solution to irregular 2Dmesh topology for NoC. The key features of the proposed Mix Router are its suitability for 2Dmesh NoC topology and its capability of suorting both full-adaptive routing and deterministic routing algorithm.

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