TFBN: A Cost Effective High Performance Hierarchical Interconnection Network

In order to fulfill the increasing demand for computation power to process a boundless data concurrently within a very short time or real-time in many areas such as IoT, AI, machine learning, smart grid, and big data analytics, we need exa-scale or zetta-scale computation in the near future. Thus, to have this level of computation, we need a massively parallel computer (MPC) system that shall consist of millions of nodes; and, for the interconnection of these massive numbers of nodes, conventional topologies are infeasible. Thus, a hierarchical interconnection network (HIN) is a rational way to connect huge nodes. Through this article, we are proposing a new HIN, which is a tori-connected flattened butterfly network (TFBN) for the next generation MPC system. Numerous basic modules are hierarchically interconnected as a toroidal connection, whereby the basic modules are flattened butterfly networks. We have studied the network architecture, static network performance, and static cost-effectiveness of the proposed TFBN in detail; and compared static network and cost-effectiveness performance of the TFBN to those of TTN, torus, TESH, and mesh networks. It is depicted that TFBN possesses low diameter and average distance, high arc connectivity, and temperate bisection width. It also has better cost-effectiveness and cost-performance trade-off factor compared to those of TTN, torus, TESH, and mesh networks. The only shortcoming is that the complexity of wiring of the TFBN is higher than that of those networks; this is because the basic module necessitates some extra short length link to form the flattened butterfly network. Therefore, TFBN is a high performance and cost-effective HIN, and it will be a good option for the next generation MPC system.

A New Cost Effective and Reliable Interconnection Topology for Parallel Computing Systems

Topology of the of interconnection network is one of the most important considerations in the design of parallel systems as it is the backbone network over which the different components of the computer communicate with each other. The properties of the topology such as connectivity, reliability, cost, fault tolerance, diameter and bisection width determine the flawless-less data transmission between the source and the sink nodes. In this paper, we propose a new hybrid interconnection network topology called TOR-CUBE (TC) which is a product of two classical popular interconnection topologies namely hypercube and torus. Further, we show the construction and characteristics of the proposed interconnection topology. We also presented some basic important properties and formulated two routing algorithms for TC. Our results show that the proposed interconnection topology has high connectivity, lesser diameter, low cost, fault tolerant, scalable and low average distance. The different reliability measures of TC are computed and found to be better as compared with its counterpart topologies and the parent topologies.

Architecture and Network-on-Chip Implementation of a New Hierarchical Interconnection Network

A Midimew-connected Mesh Network (MMN) is a minimal distance mesh with wrap-around links network of multiple basic modules (BMs), in which the BMs are 2D-mesh networks that are hierarchically interconnected for higher-level networks. In this paper, we present the architecture of the MMN, addressing of node, routing of message, and evaluate the static network performance of MMN, TESH, mesh and torus networks. In addition, we propose the network-on-chip (NoC) implementation of MMN. With innovative combination of diagonal and hierarchical structure, the MMN possesses several attractive features, including constant degree, small diameter, low cost, small average distance, moderate bisection width and high fault tolerant performance than that of other conventional and hierarchical interconnection networks. The simple architecture of MMN is also highly suitable for NoC implementation. To implement all the links of level-3 MMN, only four layers are needed which is feasible with current and future VLSI technologies.