scholarly journals Design and implementation of secured agent based NoC using shortest path routing algorithm

2019 ◽  
Vol 9 (2) ◽  
pp. 950
Author(s):  
Kendaganna Swamy S ◽  
Anand Jatti ◽  
Uma B. V.
Keyword(s):  
Shortest Path ◽  
High Performance ◽  
Fault Tolerant ◽  
Routing Algorithm ◽  
System On Chip ◽  
Multiprocessor System ◽  
Shortest Path Routing ◽  
Agent Based ◽  
On Chip ◽  
Fault Information

Network on chip (NoC) is a scalable interconnection architecture for every increasing communication demand between many processing cores in system on chip design. Reliability aspects are becoming an important issue in fault tolerant architecture. Hence there is a demand for fault tolerant Agent architecture with suitable routing algorithm which plays a vital role in order to enhance the NoC performance. The proposed fault tolerant Agent based NoC method is used to enhance the reliability and performance of the Multiprocessor System on Chip (MPSoC) design against faulty links and nodes. These agents are placed in hierarchical manner to collect, process, classify and distribute different fault information related to the faulty links and nodes of the network. This fault information is used for further packet routing in the network with the help of shortest path routing algorithm. In addition to this the agent will provide the security for the node by setting firewall, which then decides whether the packet has to be processed or not. This intern provides high performance, low latency NoC by avoiding deadlock and live lock with low area overhead.

scholarly journals Reconfigurable High Performance Secured NoC Design Using Hierarchical Agent-based Monitoring System

2018 ◽  
Vol 8 (6) ◽  
pp. 4164
Author(s):  
Kendaganna Swamy S ◽  
Anand Jatti ◽  
Uma B. V
Keyword(s):  
Monitoring System ◽  
High Performance ◽  
Fault Tolerant ◽  
Routing Algorithm ◽  
Data Communication ◽  
Multiprocessor System ◽  
Packet Routing ◽  
Distributed Agents ◽  
Agent Based ◽  
On Chip

With the rapid increase in demand for high performance computing, there is also a significant growth of data communication that leads to leverage the significance of network on chip. This paper proposes a reconfigurable fault tolerant on chip architecture with hierarchical agent based monitoring system for enhancing the performance of network based multiprocessor system on chip against faulty links and nodes. These distributed agents provide healthy status and congestion information of the network. This status information is used for further packet routing in the network with the help of XY routing algorithm. The functionality of Agent is enhanced not only to work as information provider but also to take decision for packet to either pass or stop to the processing element by setting the firewall in order to provide security. Proposed design provides a better performance and area optimization by avoiding deadlock and live lock as compared to existing approaches over network design.

A high performance scalable fuzzy based modified Asymmetric Heterogene Multiprocessor System on Chip (AHt-MPSOC) reconfigurable architecture

2021 ◽  
pp. 1-12
Author(s):  
Arun Prasath Raveendran ◽  
Jafar A. Alzubi ◽  
Ramesh Sekaran ◽  
Manikandan Ramachandran
Keyword(s):  
High Performance ◽  
Standard Technique ◽  
System On Chip ◽  
Mixed Integer ◽  
Multiprocessor System ◽  
Compound System ◽  
Available Bandwidth ◽  
Mip Model ◽  
Fpga Chip ◽  
On Chip

This Ensuing generation of FPGA circuit tolerates the combination of lot of hard and soft cores as well as devoted accelerators on a chip. The Heterogene Multi-Processor System-on-Chip (Ht-MPSoC) architecture accomplishes the requirement of modern applications. A compound System on Chip (SoC) system designed for single FPGA chip, and that considered for the performance/power consumption ratio. In the existing method, a FPGA based Mixed Integer Programming (MIP) model used to define the Ht-MPSoC configuration by taking into consideration the sharing hardware accelerator between the cores. However, here, the sharing method differs from one processor to another based on FPGA architecture. Hence, high number of hardware resources on a single FPGA chip with low latency and power targeted. For this reason, a fuzzy based MIP and Graph theory based Traffic Estimator (GTE) are proposed system used to define New asymmetric multiprocessor heterogene framework on microprocessor (AHt-MPSoC) architecture. The bandwidths, energy consumption, wait and transmission range are better accomplished in this suggested technique than the standard technique and it is also implemented with a multi-task framework. The new Fuzzy control-based AHt-MPSoC analysis proves significant improvement of 14.7 percent in available bandwidth and 89.8 percent of energy minimized to various traffic scenarios as compared to conventional method.

Design of Router Supporting Multiply Routing Algorithm for NoC

2014 ◽  
Vol 981 ◽  
pp. 431-434
Author(s):  
Zhan Peng Jiang ◽  
Rui Xu ◽  
Chang Chun Dong ◽  
Lin Hai Cui
Keyword(s):  
Complex System ◽  
High Performance ◽  
Routing Algorithm ◽  
Network On Chip ◽  
System On Chip ◽  
Low Latency ◽  
Deterministic Routing ◽  
Key Features ◽  
Design Challenge ◽  
On Chip

Network on Chip(NoC)，a new proposed solution to solve global communication problem in complex System on Chip (SoC) design，has absorbed more and more researchers to do research in this area. Due to some distinct characteristics, NoC is different from both traditional off-chip network and traditional on-chip bus，and is facing with the huge design challenge. NoC router design is one of the most important issues in NoC system. The paper present a high-performance, low-latency two-stage pipelined router architecture suitable for NoC designs and providing a solution to irregular 2Dmesh topology for NoC. The key features of the proposed Mix Router are its suitability for 2Dmesh NoC topology and its capability of suorting both full-adaptive routing and deterministic routing algorithm.

scholarly journals Shortest Path Routing Algorithm for Hierarchical Interconnection Network-on-Chip

2015 ◽  
Vol 56 ◽  
pp. 409-414 ◽  
Author(s):  
Omair Inam ◽  
Sharifa Al Khanjari ◽  
Wim Vanderbauwhede
Keyword(s):  
Shortest Path ◽  
Interconnection Network ◽  
Routing Algorithm ◽  
Network On Chip ◽  
Shortest Path Routing ◽  
On Chip

scholarly journals Congestion-Aware Routing Algorithm for NoC Using Data Packets

2021 ◽  
Vol 2021 ◽  
pp. 1-11
Author(s):  
Khurshid Ahmad ◽  
Muhammad Athar Javed Sethi ◽  
Rehmat Ullah ◽  
Imran Ahmed ◽  
Amjad Ullah ◽  
...  
Keyword(s):  
Routing Algorithm ◽  
Network On Chip ◽  
Routing Algorithms ◽  
System On Chip ◽  
Multiprocessor System ◽  
Data Packets ◽  
Communication Framework ◽  
Using Data ◽  
On Chip ◽  
Congestion Aware

Network on Chip (NoC) is a communication framework for the Multiprocessor System on Chip (MPSoC). It is a router-based communication system. In NoC architecture, nodes of MPSoC are communicating through the network. Different routing algorithms have been developed by researchers, e.g., XY, intermittent XY, DyAD, and DyXY. The main problems in these algorithms are congestion and faults. Congestion and faults cause delay, which degrades the performance of NoC. A congestion-aware algorithm is used for the distribution of traffic over NoC and for the avoidance of congestion. In this paper, a congestion-aware routing algorithm is proposed. The algorithm works by sending congestion information in the data packet. The algorithm is implemented on a 4 × 4 mesh NoC using FPGA. The proposed algorithm decreases latency, increases throughput, and uses less bandwidth in sharing congestion information between routers in comparison to the existing congestion-aware routing algorithms.

scholarly journals REVIEW OF XY ROUTING ALGORITHM FOR NETWORK-ON-CHIP ARCHITECTURE

2016 ◽  
pp. 271-275
Author(s):  
SHUBHANGI D CHAWADE ◽  
MAHENDRA A GAIKWAD ◽  
RAJENDRA M PATRIKAR
Keyword(s):  
Fault Tolerant ◽  
Routing Algorithm ◽  
Network On Chip ◽  
System On Chip ◽  
Network Resource ◽  
Key Factor ◽  
On Chip

The Network-on-Chip (NoC) is Network-version of System-on-Chip (SoC) means that on-chip communication is done through packet based networks. In NOC topology, routing algorithm and switching are main terminology .The routing algorithm is one of the key factor in NOC architecture. The routing algorithm, which defines as the path taken by a packet between the source and the destination. As XY routing algorithm mainly used in NOC because of its simplicity. This paper basically review of XY routing algorithm in which we study a different type of XY routing algorithm . The classification of XY routing algorithm is totally depend upon the environment and requirement. Such that IX/Y routing algorithm is for less collision in network ,for deadlock-free and livelock-free DyXY is used, for fault-tolerant XYX routing algorithm is proposed and Adaptive XY routing algorithm is used for fully utilization of network resource.

scholarly journals Performance Analysis of Multi-Fault Tolerant on Multiprocessor System On-chip

2019 ◽  
Vol 8 (12S2) ◽  
pp. 226-230
Keyword(s):  
Performance Analysis ◽  
Fault Tolerant ◽  
System On Chip ◽  
Multiprocessor System ◽  
Networks On Chip ◽  
On Chip ◽  
Network Interfaces ◽  
Evaluation Techniques

As plan multifaceted nature increments and scale innovation into profound submicron region, the opportunity of harm and unhappiness in Networks-on-Chip (NoCs) prolonged element. On this artwork, we middle across the examination and evaluation techniques to improve the unwavering excellent and strength of Network Interfaces (NIs) in multiprocessor framework on-chip engineering primarily based totally Noc. NIS is going about as an interface the various center covered innovation and interchanges foundation; incorrect conduct of one in all them can impact, ultimately, the overall framework. On this paintings, proposes a version of utilitarian mistakes for NI components to assess their helplessness to mistakes. Showing levels tolerant affiliation that may be utilized to decrease the affects of each changeless and transitory blames in NI. Display trial reenactment with limited overhead can collect NI dependability equal to the best got via manner of utilizing a framework using 3 stylish secluded repetition techniques, even as putting aside to 48 percent in the place, just as growing noteworthy energy decrease.

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