A survey on fault-tolerant application mapping techniques for Network-on-Chip

Journal of Systems Architecture ◽

10.1016/j.sysarc.2018.10.001 ◽

2019 ◽

Vol 92 ◽

pp. 39-52 ◽

Author(s):

Nassima Kadri ◽

Mouloud Koudil

Keyword(s):

Fault Tolerant ◽

Network On Chip ◽

Application Mapping ◽

Mapping Techniques ◽

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Fault-Tolerant Application Mapping on Mesh-of-Tree based Network-on-Chip

Journal of Systems Architecture ◽

10.1016/j.sysarc.2021.102026 ◽

2021 ◽

Vol 116 ◽

pp. 102026

Author(s):

P. Veda Bhanu ◽

Soumya J.

Keyword(s):

Fault Tolerant ◽

Network On Chip ◽

Application Mapping ◽

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Fault-Tolerant Application Mapping on to ZMesh topology based Network-on-Chip Design

2020 15th IEEE Conference on Industrial Electronics and Applications (ICIEA) ◽

10.1109/iciea48937.2020.9248099 ◽

2020 ◽

Author(s):

P. Veda Bhanu ◽

Nikita Mandapati ◽

Soumya J ◽

Linga Reddy Cenkeramaddi

Keyword(s):

Fault Tolerant ◽

Network On Chip ◽

Chip Design ◽

Application Mapping ◽

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A fault-tolerant network-on-chip design using dynamic reconfiguration of partial-faulty routing resources

2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip ◽

10.1109/vlsisoc.2011.6081674 ◽

2011 ◽

Author(s):

Zhiliang Qian ◽

Ying Fei Teh ◽

Chi-Ying Tsui

Keyword(s):

Fault Tolerant ◽

Dynamic Reconfiguration ◽

Network On Chip ◽

Chip Design ◽

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Power density aware application mapping in mesh-based network-on-chip architecture: An evolutionary multi-objective approach

Integration ◽

10.1016/j.vlsi.2021.08.008 ◽

2021 ◽

Author(s):

Nizar Dahir ◽

Ammar Karkar ◽

Maurizio Palesi ◽

Terrence Mak ◽

Alex Yakovlev

Keyword(s):

Power Density ◽

Network On Chip ◽

Multi Objective ◽

Application Mapping ◽

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Fault-tolerant network interface for spatial division multiplexing based Network-on-Chip

7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC) ◽

10.1109/recosoc.2012.6322894 ◽

2012 ◽

Author(s):

Anup Das ◽

Akash Kumar ◽

Bharadwaj Veeravalli

Keyword(s):

Fault Tolerant ◽

Network On Chip ◽

Network Interface ◽

On Chip ◽

Spatial Division Multiplexing

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A General, Fault tolerant, Adaptive, Deadlock-free Routing Protocol for Network-on-chip

2018 11th International Workshop on Network on Chip Architectures (NoCArc) ◽

10.1109/nocarc.2018.8541212 ◽

2018 ◽

Author(s):

Pieter Stroobant ◽

Sergi Abadal ◽

Wouter Tavernier ◽

Eduard Alarcon ◽

Didier Colle ◽

...

Keyword(s):

Routing Protocol ◽

Fault Tolerant ◽

Network On Chip ◽

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Application Mapping on Network-on-Chip

Network-on-Chip ◽

10.1201/9781315216072-5 ◽

2018 ◽

pp. 119-154

Author(s):

Santanu Kundu ◽

Santanu Chattopadhyay

Keyword(s):

Network On Chip ◽

Application Mapping ◽

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LPNet: A DNN based latency prediction technique for application mapping in Network-on-Chip design

Microprocessors and Microsystems ◽

10.1016/j.micpro.2021.104370 ◽

2021 ◽

pp. 104370

Author(s):

Sambangi Ramesh ◽

Manghnani Hitesh ◽

Santanu Chattopadhyay

Keyword(s):

Network On Chip ◽

Chip Design ◽

Application Mapping ◽

Prediction Technique ◽

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Multi-application Based Fault-Tolerant Network-on-Chip Design for Mesh Topology Using Reconfigurable Architecture

Communications in Computer and Information Science - VLSI Design and Test ◽

10.1007/978-981-32-9767-8_37 ◽

2019 ◽

pp. 442-454

Author(s):

P. Veda Bhanu ◽

Pranav V. Kulkarni ◽

Sai Pranavi Avadhanam ◽

J. Soumya ◽

Linga Reddy Cenkeramaddi

Keyword(s):

Fault Tolerant ◽

Network On Chip ◽

Reconfigurable Architecture ◽

Chip Design ◽

Mesh Topology ◽

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Fault-Tolerant Application-Specific Network-on-Chip Design using Discrete Particle Swarm Optimization

2019 14th Conference on Industrial and Information Systems (ICIIS) ◽

10.1109/iciis47346.2019.9063339 ◽

2019 ◽

Author(s):

P. Veda Bhanu ◽

J. Soumya

Keyword(s):

Particle Swarm Optimization ◽

Fault Tolerant ◽

Particle Swarm ◽

Network On Chip ◽

Discrete Particle Swarm Optimization ◽

Chip Design ◽

Swarm Optimization ◽

Discrete Particle ◽

On Chip ◽

Application Specific

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