Test and diagnosis pattern generation for distinguishing stuck-at faults and bridging faults

Integration ◽  
2021 ◽  
Author(s):  
Navya Mohan ◽  
J.P. Anita
2006 ◽  
Vol 22 (1) ◽  
pp. 61-69 ◽  
Author(s):  
Piet Engelke ◽  
Ilia Polian ◽  
Michel Renovell ◽  
Bernd Becker

2019 ◽  
Vol 28 (14) ◽  
pp. 1950240
Author(s):  
Hossein Mokhtarnia ◽  
Shahram Etemadi Borujeni ◽  
Mohammad Saeed Ehsani

Automatic test pattern generation (ATPG) is one of the important issues in testing digital circuits. Due to considerable advances made in the past two decades, the ATPG algorithms that are based on Boolean satisfiability have become an integral part of the digital circuits. In this paper, a new method for ATPG for testing bridging faults is introduced. First of all, the application of Boolean satisfiability to circuit modeling is explained. Afterwards, a new method of testing the nonfeedback bridging faults in the combinational circuits is proposed based on Boolean satisfiability. In the proposed method, the faulty circuit is obtained by injecting the faulty gate into the main circuit. Afterwards, the final differential circuit is prepared by using the fault-free and the faulty circuits. Finally, using the resulting differential circuit, the testability of the fault is assessed and the input pattern for detecting the fault in the main circuit is derived. The experimental results presented at the end of this paper indicate the effectiveness and usefulness of this method for testing the bridging faults.


VLSI Design ◽  
1998 ◽  
Vol 7 (2) ◽  
pp. 163-176 ◽  
Author(s):  
Gerald Spiegel ◽  
Albrecht P. Stroele

Fault sets that accurately describe physical failures are required for efficient pattern generation and fault coverage evaluation. The fault model presented in this paper uniquely describes all structural changes in the transistor net list that can be caused by spot defects, including bridging faults that connect more than two nets, break faults that break a net into more than two parts, and compound faults. The developed analysis method extracts the comprehensive set of realistic faults from the layout of CMOS ICs and for each fault computes the probability of occurrence. The results obtained by the tool REFLEX show that bridging faults connecting more than two nets account for a significant portion of all faults and cannot be neglected.


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