Plasmonic Color Filters for CMOS Image Sensor Applications

Nano Letters ◽  
2012 ◽  
Vol 12 (8) ◽  
pp. 4349-4354 ◽  
Author(s):  
Sozo Yokogawa ◽  
Stanley P. Burgos ◽  
Harry A. Atwater
Nano Letters ◽  
2017 ◽  
Vol 17 (5) ◽  
pp. 3159-3164 ◽  
Author(s):  
Yu Horie ◽  
Seunghoon Han ◽  
Jeong-Yub Lee ◽  
Jaekwan Kim ◽  
Yongsung Kim ◽  
...  

2021 ◽  
Vol 29 (3) ◽  
pp. 3643
Author(s):  
Jongwoo Hong ◽  
Hyunwoo Son ◽  
Changhyun Kim ◽  
Sang-Eun Mun ◽  
Jangwoon Sung ◽  
...  

2016 ◽  
Vol 24 (14) ◽  
pp. 16027 ◽  
Author(s):  
Jong-Kwon Lee ◽  
Ahreum Kim ◽  
Dong-Wan Kang ◽  
Byung Yang Lee

Author(s):  
Jin-Yi Lin ◽  
Kwuang-Han Chang ◽  
Chen-Che Kao ◽  
Shih-Chin Lo ◽  
Yan-Jiun Chen ◽  
...  

2011 ◽  
Vol 19 (14) ◽  
pp. 13073 ◽  
Author(s):  
Laurent Frey ◽  
Pascale Parrein ◽  
Jacques Raby ◽  
Catherine Pellé ◽  
Didier Hérault ◽  
...  

Sensors ◽  
2020 ◽  
Vol 20 (3) ◽  
pp. 727
Author(s):  
Francois Roy ◽  
Andrej Suler ◽  
Thomas Dalleau ◽  
Romain Duru ◽  
Daniel Benoit ◽  
...  

Tackling issues of implantation-caused defects and contamination, this paper presents a new complementary metal–oxide–semiconductor (CMOS) image sensor (CIS) pixel design concept based on a native epitaxial layer for photon detection, charge storage, and charge transfer to the sensing node. To prove this concept, a backside illumination (BSI), p-type, 2-µm-pitch pixel was designed. It integrates a vertical pinned photo gate (PPG), a buried vertical transfer gate (TG), sidewall capacitive deep trench isolation (CDTI), and backside oxide–nitride–oxide (ONO) stack. The designed pixel was fabricated with variations of key parameters for optimization. Testing results showed the following achievements: 13,000 h+ full-well capacity with no lag for charge transfer, 80% quantum efficiency (QE) at 550-nm wavelength, 5 h+/s dark current at 60 °C, 2 h+ temporal noise floor, and 75 dB dynamic range. In comparison with conventional pixel design, the proposed concept could improve CIS performance.


2017 ◽  
Author(s):  
S.-K. Park ◽  
D. Woo ◽  
M.-K. Na ◽  
P.-S. Kwag ◽  
H.-R. Lee ◽  
...  

2017 ◽  
Vol 137 (2) ◽  
pp. 48-58
Author(s):  
Noriyuki Fujimori ◽  
Takatoshi Igarashi ◽  
Takahiro Shimohata ◽  
Takuro Suyama ◽  
Kazuhiro Yoshida ◽  
...  

2020 ◽  
Vol 2020 (7) ◽  
pp. 143-1-143-6 ◽  
Author(s):  
Yasuyuki Fujihara ◽  
Maasa Murata ◽  
Shota Nakayama ◽  
Rihito Kuroda ◽  
Shigetoshi Sugawa

This paper presents a prototype linear response single exposure CMOS image sensor with two-stage lateral overflow integration trench capacitors (LOFITreCs) exhibiting over 120dB dynamic range with 11.4Me- full well capacity (FWC) and maximum signal-to-noise ratio (SNR) of 70dB. The measured SNR at all switching points were over 35dB thanks to the proposed two-stage LOFITreCs.


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