Estimation of energy consumption and execution time in early phases of design lifecycle: an application to biomedical systems

As mobile devices become more and more powerful, applications generate a large number of computing tasks, and mobile devices themselves cannot meet the needs of users. This article proposes a computation offloading model in which execution units including mobile devices, edge server, and cloud server. Previous studies on joint optimization only considered tasks execution time and the energy consumption of mobile devices, and ignored the energy consumption of edge and cloud server. However, edge server and cloud server energy consumption have a significant impact on the final offloading decision. This paper comprehensively considers execution time and energy consumption of three execution units, and formulates task offloading decision as a single-objective optimization problem. Genetic algorithm with elitism preservation and random strategy is adopted to obtain optimal solution of the problem. At last, simulation experiments show that the proposed computation offloading model has lower fitness value compared with other computation offloading models.

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Research on Network-on-Chip Dynamic and Adaptive Algorithm and Choice Strategy

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.539.296 ◽

2014 ◽

Vol 539 ◽

pp. 296-302

Author(s):

Dong Li

Keyword(s):

Energy Consumption ◽

Execution Time ◽

Adaptive Algorithm ◽

Network On Chip ◽

Time Dimension ◽

Choice Strategy ◽

Bus Structure ◽

On Chip ◽

Mapping Scheme ◽

Single Objective

With further increase of the number of on-chip device, the bus structure has not met the requirements. In order to make better communication between each part, the chip designers need to explore a new structure to solve the interconnection of on-chip device. The paper proposes a network-on-chip dynamic and adaptive algorithm which selects NoC platform with 2-dimension mesh as the carrier, incorporates communication energy consumption and delay into unified cost function and uses ant colony optimization to realize NOC map facing energy consumption and delay. The experiment indicates that compared with random map, single objective optimization can separately saves (30%~47 %) and ( 20%~39%) in communication energy consumption and execution time compared with random map, and joint objective optimization can further excavate the potential of time dimension in mapping scheme dominated by the energy.

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Joint Optimization Offloading Strategy of Execution Time and Energy Consumption of Mobile Edge Computing

The International Arab Journal of Information Technology ◽

10.34028/iajit/18/5/11 ◽

2021 ◽

Vol 18 (5) ◽

Author(s):

Qingzhu Wang ◽

Xiaoyun Cui

Keyword(s):

Energy Consumption ◽

Execution Time ◽

Edge Computing ◽

Joint Optimization ◽

Mobile Edge Computing ◽

Time And Energy

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A methodology correlating code optimizations with data memory accesses, execution time and energy consumption

The Journal of Supercomputing ◽

10.1007/s11227-019-02880-z ◽

2019 ◽

Vol 75 (10) ◽

pp. 6710-6745 ◽

Cited By ~ 1

Author(s):

Vasilios Kelefouras ◽

Karim Djemame

Keyword(s):

Energy Consumption ◽

Execution Time ◽

Data Memory ◽

Memory Accesses ◽

Time And Energy ◽

Code Optimizations

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Creating Customized CGRAs for Scientific Applications

Electronics ◽

10.3390/electronics10040445 ◽

2021 ◽

Vol 10 (4) ◽

pp. 445

Author(s):

George Charitopoulos ◽

Ioannis Papaefstathiou ◽

Dionisios N. Pnevmatikatos

Keyword(s):

Energy Consumption ◽

Execution Time ◽

Coarse Grain ◽

Scientific Applications ◽

Cell Array ◽

Analysis Methods ◽

Reconfigurable Arrays ◽

Hardware Implementations ◽

Application Analysis ◽

Software Implementations

Executing complex scientific applications on Coarse Grain Reconfigurable Arrays (CGRAs) offers improvements in the execution time and/or energy consumption when compared to optimized software implementations or even fully customized hardware solutions. In this work, we explore the potential of application analysis methods in such customized hardware solutions. We offer analysis metrics from various scientific applications and tailor the results that are to be used by MC-Def, a novel Mixed-CGRA Definition Framework targeting a Mixed-CGRA architecture that leverages the advantages of CGRAs and those of FPGAs by utilizing a customized cell-array along, with a separate LUT array being used for adaptability. Additionally, we present the implementation results regarding the VHDL-created hardware implementations of our CGRA cell concerning various scientific applications.

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Exploring Direct Convolution Performance on the Gemmini Accelerator

10.5753/wscad.2020.14067 ◽

2020 ◽

Author(s):

Caio Vieira ◽

Arthur Lorenzon ◽

Lucas Schnorr ◽

Philippe Navaux ◽

Antonio Carlos Beck

Keyword(s):

Neural Network ◽

Computer Vision ◽

Energy Consumption ◽

Convolutional Neural Network ◽

Building Block ◽

Execution Time ◽

Performance Gap ◽

Main Building ◽

Time And Energy ◽

Lower Frequencies

Convolutional Neural Network (CNN) algorithms are becoming a recurrent solution to solve Computer Vision related problems. These networks employ convolutions as main building block, which greatly impact their performance since convolution is a costly operation. Due to its importance in CNN algorithms, this work evaluates convolution performance in the Gemmini accelerator and compare it to a conventional lightlyand heavily-loaded desktop CPU in terms of execution time and energy consumption. We show that Gemmini can achieve lower execution time and energy consumption when compared to a CPU even for small convolutions, and this performance gap grows with convolution size. Furthermore, we analyze the minimum Gemmini required frequency to match the same CPU execution time, and show that Gemmini can achieve the same runtime while working in much lower frequencies.

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