Gut Microbiota and Mycobiota Evolution Is Linked to Memory Improvement after Bariatric Surgery in Obese Patients: A Pilot Study

Patients with obesity are known to exhibit gut microbiota dysbiosis and memory deficits. Bariatric surgery (BS) is currently the most efficient anti-obesity treatment and may improve both gut dysbiosis and cognition. However, no study has investigated association between changes of gut microbiota and cognitive function after BS. We prospectively evaluated 13 obese patients on anthropometric data, memory functions, and gut microbiota-mycobiota before and six months after BS. The Rey Auditory Verbal Learning Test (AVLT) and the symbol span (SS) of the Weschler Memory Scale were used to assess verbal and working memory, respectively. Fecal microbiota and mycobiota were longitudinally analyzed by 16S and ITS2 rRNA sequencing respectively. AVLT and SS scores were significantly improved after BS (AVLT scores: 9.7 ± 1.7 vs. 11.2 ± 1.9, p = 0.02, and SS scores: 9.7 ± 23.0 vs. 11.6 ± 2.9, p = 0.05). An increase in bacterial alpha-diversity, and Ruminococcaceae, Prevotella, Agaricus, Rhodotorula, Dipodascus, Malassezia, and Mucor were significantly associated with AVLT score improvement after BS, while an increase in Prevotella and a decrease in Clostridium, Akkermansia, Dipodascus and Candida were linked to SS scores improvement. We identified several changes in the microbial communities that differ according to the improvement of either the verbal or working memories, suggesting a complex gut-brain-axis that evolves after BS.

Measuring the dynamic energy efficiency of FPGAs over processors

This work investigates the dynamic energy efficiency of the parallel execution model of an FPGA and the sequential execution model of a processor, for latency-insensitive applications. We create the temporal implementations (sequential instructions) of the MCNC benchmarks to be executed on a processor that employs a 4LUT as its functional unit. This processor is ~716 times inefficient for dynamic energy than a 4LUT FPGA, mainly due to the large amount of memory (instruction/data) that is required to encode the 4LUT based instructions. The size of the memory (instruction/data) can be reduced by increasing the data-path width and the logic complexity of the ASIC-based functional units of the processor. Particularly, at 64-bit data-path width and when the (instruction/data) memory sizes are reduced to less than ~9% of their corresponding 4LUT-based instructions, the processor with ASIC-based complex functional unit can achieve higher dynamic energy efficiency than the FPGA for MCNC benchmarks.

Measuring the dynamic energy efficiency of FPGAs over processors

This work investigates the dynamic energy efficiency of the parallel execution model of an FPGA and the sequential execution model of a processor, for latency-insensitive applications. We create the temporal implementations (sequential instructions) of the MCNC benchmarks to be executed on a processor that employs a 4LUT as its functional unit. This processor is ~716 times inefficient for dynamic energy than a 4LUT FPGA, mainly due to the large amount of memory (instruction/data) that is required to encode the 4LUT based instructions. The size of the memory (instruction/data) can be reduced by increasing the data-path width and the logic complexity of the ASIC-based functional units of the processor. Particularly, at 64-bit data-path width and when the (instruction/data) memory sizes are reduced to less than ~9% of their corresponding 4LUT-based instructions, the processor with ASIC-based complex functional unit can achieve higher dynamic energy efficiency than the FPGA for MCNC benchmarks.

Robust high-dimensional memory-augmented neural networks

Traditional neural networks require enormous amounts of data to build their complex mappings during a slow training procedure that hinders their abilities for relearning and adapting to new data. Memory-augmented neural networks enhance neural networks with an explicit memory to overcome these issues. Access to this explicit memory, however, occurs via soft read and write operations involving every individual memory entry, resulting in a bottleneck when implemented using the conventional von Neumann computer architecture. To overcome this bottleneck, we propose a robust architecture that employs a computational memory unit as the explicit memory performing analog in-memory computation on high-dimensional (HD) vectors, while closely matching 32-bit software-equivalent accuracy. This is achieved by a content-based attention mechanism that represents unrelated items in the computational memory with uncorrelated HD vectors, whose real-valued components can be readily approximated by binary, or bipolar components. Experimental results demonstrate the efficacy of our approach on few-shot image classification tasks on the Omniglot dataset using more than 256,000 phase-change memory devices. Our approach effectively merges the richness of deep neural network representations with HD computing that paves the way for robust vector-symbolic manipulations applicable in reasoning, fusion, and compression.

DARE: A decentralized association rules extraction scheme for embedded data sets in distributed IoT devices

In the context of smart home, it is very important to identify usage patterns of Internet of things (IoT) devices. Finding these patterns and using them for decision-making can provide ease, comfort, practicality, and autonomy when executing daily activities. Performing knowledge extraction in a decentralized approach is a computational challenge considering the tight storage and processing constraints of IoT devices, unlike deep learning, which demands a massive amount of data, memory, and processing capability. This article describes a method for mining implicit correlations among the actions of IoT devices through embedded associative analysis. Based on support, confidence, and lift metrics, our proposed method identifies the most relevant correlations between a pair of actions of different IoT devices and suggests the integration between them through hypertext transfer protocol requests. We have compared our proposed method with a centralized method. Experimental results show that the most relevant rules for both methods are the same in 99.75% of cases. Moreover, our proposed method was able to identify relevant correlations that were not identified by the centralized one. Thus, we show that associative analysis of IoT device state change is efficient to provide an intelligent and highly integrated IoT platform while avoiding the single point of failure problem.

Hardware description of a simplified 4-bit softcore processor with BCD capabilities

The objective of the work reported in this paper is to improve a 4-bit softcore processor previously designed in Verilog language, keeping its compact size. This processor was thought to be used as academic and didactic tool for teaching as computers architecture subject as digital circuits subject in the technology faculty of the Universidad Distrital. The new features include arithmetic instruction with input carry, BCD operations enabling, rotating instructions, implementation of input and output register banks, increase of the number of general purpose registers of the data memory, and the reduction of the execution clock cycles per instruction. Additionally, the assembler software was enabled to support macro-instructions to make easy the comprehension of some composed functions. As result, a very compact softcore processor was obtained, by means of a Verilog description done in a single file. This implementation occupies only the 2% of the medium-size FPGA used for the application, reaching a maximum possible working clock frequency of 929 Mhz.

Rancang Bangun Pengembangan Sistem Controller Processing Station pada Factory Trainer di Laboratorium Mekatronika Program Studi Teknik Elektronika

Otomatisasi sangat dibutuhkan dalam kehidupan initerutama dalam dunia perindustrian. Seiring dengan kemajuanzaman yang menuntut pekerjaan manusia menjadi lebih efektifdan efisien, maka diperlukan sebuah sistem otomatisasi. Sistemini sangat berguna meningkatkan suatu target dalam industri danmemudahkan manusia untuk mengontrol alat-alat dalam sebuahproses produksi. Dengan rancang bangun pengembangan con-troller mini factory trainer processing station diimplementasikanjuga dengan sistem SCADA dan juga pembuatan wiring diagramsistem controller processing station dirancang dengan menggu-nakan PLC Omron CP1E-N40 sebagai sistem pengendali darimini factory processing station. Pada perancangan akan dibuatprogram pengendali dan pengawasan terhadap plant processingstation. Diharapkan sistem controller dapat berkomunikasi den-gan HMI yang mengontrol plant. Percobaan dapat diaplikasikandengan menguji perbedaan interval waktu antara PLC CP1Etype E dengan PLC CP1E type N. Hasil yang didapatkan adalahterjadi perbedaan waktu antara 0,9 detik sampai 0,12 detik.Hal ini dikarenakan adanya perbedaan kapasitas program dankapasitas data memory dari PLC CP1E type E dengan PLC CP1Etype N.