Real‐time unified architecture for forward/inverse discrete cosine transform in high efficiency video coding

2017 ◽  
Vol 11 (4) ◽  
pp. 381-387 ◽  
Author(s):  
Maher Abdelrasoul ◽  
Mohammed S. Sayed ◽  
Victor Goulart
Keyword(s):  
Video Coding ◽  
Real Time ◽  
Discrete Cosine Transform ◽  
High Efficiency ◽  
High Efficiency Video Coding ◽  
Cosine Transform ◽  
Inverse Discrete Cosine Transform

scholarly journals Steerable-Discrete-Cosine-Transform (SDCT): Hardware Implementation and Performance Analysis

Sensors ◽  
2020 ◽  
Vol 20 (5) ◽  
pp. 1405 ◽  
Author(s):  
Riccardo Peloso ◽  
Maurizio Capra ◽  
Luigi Sole ◽  
Massimo Ruo Roch ◽  
Guido Masera ◽  
...  
Keyword(s):  
Video Coding ◽  
Discrete Cosine Transform ◽  
Video Compression ◽  
High Efficiency ◽  
Frame Rate ◽  
High Efficiency Video Coding ◽  
Cosine Transform ◽  
Coding Efficiency ◽  
And Performance ◽  
Efficient Video

In the last years, the need for new efficient video compression methods grown rapidly as frame resolution has increased dramatically. The Joint Collaborative Team on Video Coding (JCT-VC) effort produced in 2013 the H.265/High Efficiency Video Coding (HEVC) standard, which represents the state of the art in video coding standards. Nevertheless, in the last years, new algorithms and techniques to improve coding efficiency have been proposed. One promising approach relies on embedding direction capabilities into the transform stage. Recently, the Steerable Discrete Cosine Transform (SDCT) has been proposed to exploit directional DCT using a basis having different orientation angles. The SDCT leads to a sparser representation, which translates to improved coding efficiency. Preliminary results show that the SDCT can be embedded into the HEVC standard, providing better compression ratios. This paper presents a hardware architecture for the SDCT, which is able to work at a frequency of 188 M Hz , reaching a throughput of 3.00 GSample/s. In particular, this architecture supports 8k UltraHigh Definition (UHD) (7680 × 4320) with a frame rate of 60 Hz , which is one of the best resolutions supported by HEVC.

scholarly journals Discrete Sine Transform-Based Interpolation Filter for Video Compression

2017 ◽  
Author(s):  
MyungJun Kim ◽  
Yung-Lyul Lee
Keyword(s):  
Video Coding ◽  
Discrete Cosine Transform ◽  
Video Compression ◽  
High Efficiency ◽  
Random Access ◽  
High Efficiency Video Coding ◽  
Interpolation Filter ◽  
Interpolation Filters ◽  
Low Delay ◽  
Sine Transform

High Efficiency Video Coding (HEVC) uses an 8-point filter and a 7-point filter, which are based on the discrete cosine transform (DCT), for the 1/2-pixel and 1/4-pixel interpolations, respectively. In this paper, discrete sine transform (DST)-based interpolation filters (IF) are proposed. The first proposed DST-based IFs (DST-IFs) use 8-point and 7-point filters for the 1/2-pixel and 1/4-pixel interpolations, respectively. The final proposed DST-IFs use 12-point and 11-point filters for the 1/2-pixel and 1/4-pixel interpolations, respectively. These DST-IF methods are proposed to improve the motion-compensated prediction in HEVC. The 8-point and 7-point DST-IF methods showed average BD-rate reductions of 0.7% and 0.3% in the random access (RA) and low delay B (LDB) configurations, respectively. The 12-point and 11-point DST-IF methods showed average BD-rate reductions of 1.4% and 1.2% in the RA and LDB configurations for the Luma component, respectively.

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