While copper interconnect scaling is approaching its fundamental physical limit, increasing wire resistivity and delay have greatly limited the circuit miniaturization. The emerging carbon nanotube (CNT) interconnects, especially single-walled CNTs (SWCNTs) bundle interconnects, have become a promising replacement material. Nevertheless, physical design optimization techniques are still needed to allow them achieving the desired performances. While the preliminary conference version of this work [L. Liu, Y. Zhou and S. Hu, Proc. IEEE Computer Society Annual Symp. on VLSI (ISVLSI), 2014] designs the first timing driven buffer insertion technique for SWCNT interconnects, it only considers resistive and capacitive effects but not inductive effects. Although inductance could be negligible for prevailing CNT-based circuit designs, it becomes important when designing ultra-high performance chips in the future. Thus, this paper considers buffering inductive bundled SWCNTs interconnects through developing a dynamic programming algorithm for buffer insertion using the RLC tree delay model. Our experiments demonstrate that bundled SWCNTs interconnect-based buffering can effectively reduce the delay by over [Formula: see text] when inductive effects are considered. With the same timing constraint, bundled SWCNTs interconnect-based buffering can save over 20% buffer area compared to copper interconnect based buffering, while still running about [Formula: see text] faster.
