scholarly journals General earth fault protection for MV networks using wavelet decomposition and Bayesian criterion

2019 ◽  
Vol 84 ◽  
pp. 02007
Author(s):  
Lubomir Marciniak
Keyword(s):  
High Resistance ◽  
Wavelet Decomposition ◽  
Harmonic Distortion ◽  
Sampling Frequency ◽  
Selective Detection ◽  
Medium Voltage ◽  
Bayesian Criterion ◽  
Fault Protection ◽  
Probability Criterion ◽  
Short Circuits

For selective detection of earth faults in medium voltage networks, the general protection can be used, which unlike individual protections controls earth currents in all lines supplied from the substation. To detect high-resistance and arc faults, it is possible to use in such protections the details from wavelet decomposition of earth currents and the Bayesian conditional probability criterion. The paper presents a protection model using details of earth currents and the Bayesian criterion. Significant parameters of the model were determined: sampling frequency, wavelet types and decomposition levels, parameters of the probability density function and decision conditions. The effectiveness of the protection in the case of non-stationary high-resistance short-circuits in the network with natural asymmetry and harmonic distortion was also assessed.

scholarly journals Performance Research of Seven Level Multi-Level Inverter with Reduced Switches using Various PWM Techniques

2019 ◽  
Vol 8 (2S8) ◽  
pp. 1149-1154
Keyword(s):  
High Power ◽  
Harmonic Distortion ◽  
Total Harmonic Distortion ◽  
Switching Topology ◽  
Switching Loss ◽  
Medium Voltage ◽  
Switching Losses ◽  
Multi Level ◽  
Low Efficiency ◽  
Performance Research

A inverter is basically a device that usually converts DC to AC voltage without causing any power loss, applicable to only low to medium voltage applications. But in case of medium to high power applications, it has demerits like high switching losses, reduced cost and low efficiency. To overcome these demerits a Multilevel inverter applicable to high voltage and high-power applications which have low total harmonic distortion (THD) is introduced. This paper is mainly focused on seven-level inverter with five switches and four dc sources. with low total harmonic distortion, less switching loss without adding any complexity to the circuit. The switching topology is integrated with various SPWM techniques like Phase Disposition (PD), Phase Opposition Disposition (POD) and Anti Phase Opposition Disposition (APOD). For better performance of the inverter above three PWM techniques will be compared and analyzed to find the low THD configuration. The simulation of switching topology is done by MATLAB/Simulink.

Fault Protection System for Current Source Inverter with Normally on SiC JFETs

2011 ◽  
Vol 679-680 ◽  
pp. 750-753 ◽  
Author(s):  
Jacek Rabkowski ◽  
Mariusz Zdanowski ◽  
Mietek Nowak ◽  
Roman Barlik
Keyword(s):  
Laboratory Tests ◽  
Current Source ◽  
Protection System ◽  
Current Source Inverter ◽  
Fault Protection ◽  
Short Circuits

This paper describes a simple fault protection system for Current Source Inverter built with normally-on SiC JFETs. Because all transistors are in on-state after loss of the gate drive(s) supply, list of possible fault modes is extended in reference to standard inverters. That is also why an additional normally off switch is introduced in the DC link. Operation principles of the protection system which follows the drain-source voltages of JFETs and the current of the DC link are presented. The 2kVA/100kHz model of the inverter equipped with the proposed system is validated via various laboratory tests including short-circuits and the auxiliary supply turn off.

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