scholarly journals A Novel Low Common-Mode Voltage Modulation Strategy for ANPC-5L Inverter

2020 ◽  
Vol 185 ◽  
pp. 01015
Author(s):  
Fusheng Wang ◽  
Sai Weng ◽  
Lizhong Ye ◽  
Tao Chen

In order to suppress the leakage current of the active neutral point clamed five-level (ANPC-5L) inverter, this paper proposes a novel low common-mode voltage (CMV) modulation strategy based on the space vector modulation thought. Only the 55 voltage vectors with low CMV amplitude instead of all 125 voltage vectors are utilized. The CMV amplitude is suppressed to one-twelfth of the DC bus voltage (Vdc). In the simplified five-level space vector diagram, “obtuse triangle” synthesis principle is used to control the CMV changes twice in each carrier cycle, and get lower output current total harmonic distortion (THD). According to the vector thought, a carrier implementation method based on zero sequence voltage injection and carrier splitting is proposed. This method simplifies the calculation and is easy to implement.Simulation results prove the correctness and feasibility of this low CMV modulation strategy.

2020 ◽  
Vol 29 (14) ◽  
pp. 2050229 ◽  
Author(s):  
Palanisamy Ramasamy ◽  
Vijayakumar Krishnasamy

In this paper, a three-dimensional Space Vector Modulation (3D SVM) is implemented for minimization of Common-Mode Voltage (CMV) of five-level Neutral Point Clamped (NPC) inverter. The 3D SVM control includes all merits of 2D SVM and provides better control compared to other PWM strategies. The switching state vectors are selected based on the nearest vector Switching State Vector (NSV); it selects the switching vectors which are having the minimum CMV level. It leads to minimization of the bearing voltage and protection of the drive from the damage; also this system reduces the total harmonic distortion. The switching time is calculated by reference vector identification with large and small subcubes tracking and prisms tracking in 3D cubic region. The CMV level with 3D SVM scheme is compared with other PWM methods. The simulation and hardware results are verified using Matlab Simulink and FPGA processor.


2018 ◽  
Vol 65 (10) ◽  
pp. 8340-8350 ◽  
Author(s):  
Changwei Qin ◽  
Chenghui Zhang ◽  
Alian Chen ◽  
Xiangyang Xing ◽  
Guangxian Zhang

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