scholarly journals Quantum Associative Memory in Hep Track Pattern Recognition

2019 ◽  
Vol 214 ◽  
pp. 01012 ◽  
Author(s):  
Illya Shapoval ◽  
Paolo Calafiura

We have entered the Noisy Intermediate-Scale Quantum Era. A plethora of quantum processor prototypes allow evaluation of potential of the Quantum Computing paradigm in applications to pressing computational problems of the future. Growing data input rates and detector resolution foreseen in High-Energy LHC (2030s) experiments expose the often high time and/or space complexity of classical algorithms. Quantum algorithms can potentially become the lower-complexity alternatives in such cases. In this work we discuss the potential of Quantum Associative Memory (QuAM) in the context of LHC data triggering. We examine the practical limits of storage capacity, as well as store and recall errorless efficiency, from the viewpoints of the state-of-the-art IBM quantum processors and LHC real-time charged track pattern recognition requirements. We present a software prototype implementation of the QuAM protocols and analyze the topological limitations for porting the simplest QuAM instances to the public IBM 5Q and 14Q cloud-based superconducting chips.

2020 ◽  
Vol 245 ◽  
pp. 10006
Author(s):  
Masahiko Saito ◽  
Paolo Calafiura ◽  
Heather Gray ◽  
Wim Lavrijsen ◽  
Lucy Linder ◽  
...  

The High-Luminosity Large Hadron Collider (HL-LHC) starts from 2027 to extend the physics discovery potential at the energy frontier. The HL-LHC produces experimental data with a much higher luminosity, requiring a large amount of computing resources mainly due to the complexity of a track pattern recognition algorithm. Quantum annealing might be a solution for an efficient track pattern recognition in the HL-LHC environment. We demonstrated to perform the track pattern recognition by using the D-Wave annealing machine and the Fujitsu Digital Annealer. The tracking efficiency and purity for the D-Wave quantum annealer are comparable with those for a classical simulated annealing at a low pileup condition, while a drop in performance is found at a high pileup condition, corresponding to the HL-LHC pileup environment. The tracking efficiency and purity for the Fujitsu Digital Annealer are nearly the same as the classical simulated annealing.


2011 ◽  
Author(s):  
G. Deputch ◽  
J. Hoff ◽  
R. Lipton ◽  
T. Liu ◽  
J. Olsen ◽  
...  

1966 ◽  
Vol EC-15 (6) ◽  
pp. 944-947 ◽  
Author(s):  
S. S. Yau ◽  
C. C. Yang

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