Effects of temperature and electrical stress on the performance of thin‐film transistors fabricated from undoped low‐pressure chemical vapor deposited polycrystalline silicon

1989 ◽  
Vol 54 (7) ◽  
pp. 620-622 ◽  
Author(s):  
C. A. Dimitriadis ◽  
P. A. Coxon
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Polycrystalline Silicon ◽  
Chemical Vapor ◽  
Low Pressure ◽  
Electrical Stress ◽  
Chemical Vapor Deposited ◽  
Pressure Chemical ◽  
Effects Of Temperature

Effect of annealing ambient on performance and reliability of low pressure chemical vapor deposited oxides for thin film transistors

1996 ◽  
Vol 424 ◽  
Author(s):  
N. Bhat ◽  
A. Wang ◽  
K. C. Saraswat
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Chemical Vapor ◽  
Low Pressure ◽  
Interface State ◽  
State Density ◽  
Interfacial Stress ◽  
Bias Temperature Instability ◽  
Chemical Vapor Deposited ◽  
Pressure Chemical

AbstractThe performance and reliability of low pressure chemical vapor deposited (LPCVD) oxides subjected to oxidizing, inert and nitriding annealing ambients is characterized both at low temperature (600°C) and high temperature (950°C). The oxidizing ambient results in worse initial interface state density and charge to break down. We attribute this to the interfacial stress developed during the oxidation, due to the volume mismatch between Si and SiO2. The C-V measurements on poly-Si substrate capacitors and the charge pumping measurements on poly-Si thin film transistors (TFTs) indicate lower trap density for inert and nitriding ambients. The TFTs with inert anneal exhibit lower bias temperature instability compared to oxidizing ambient.

Lateral diffusion of arsenic in low pressure chemical vapor deposited polycrystalline silicon

1983 ◽  
Vol 42 (2) ◽  
pp. 171-172 ◽  
Author(s):  
N. Lewis ◽  
G. Gildenblat ◽  
M. Ghezzo ◽  
W. Katz ◽  
G. A. Smith
Keyword(s):  
Polycrystalline Silicon ◽  
Lateral Diffusion ◽  
Chemical Vapor ◽  
Low Pressure ◽  
Chemical Vapor Deposited ◽  
Pressure Chemical
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