Influence of ana‐SiNx:H gate insulator on an amorphous silicon thin‐film transistor

1987 ◽  
Vol 62 (5) ◽  
pp. 2129-2135 ◽  
Author(s):  
Kouichi Hiranaka ◽  
Tetsuzo Yoshimura ◽  
Tadahisa Yamaguchi
1999 ◽  
Vol 558 ◽  
Author(s):  
J.Y. Nahm ◽  
J.H. Lan ◽  
J. Kanicki

ABSTRACTA high-voltage hydrogenated amorphous silicon thin film transistor (H-V a-Si:H TFT) with thick double layer gate insulator (∼0.95 μm) has been developed for reflective active-matrix cholesteric liquid crystal displays. The double layer gate insulator consists of 0.85 and 0.10 μm thick benzocyclobutene and hydrogenated amorphous silicon nitride, respectively. This HV a-Si:H TFT operates at the gate-tosource and drain-to-source biases up to 100V without any serious leakage current degradation and device breakdown.


2004 ◽  
Vol 25 (3) ◽  
pp. 132-134 ◽  
Author(s):  
S.H. Won ◽  
J.H. Hur ◽  
C.B. Lee ◽  
H.C. Nam ◽  
J.K. Chung ◽  
...  

2000 ◽  
Vol 21 (1) ◽  
pp. 18-20 ◽  
Author(s):  
Young Jin Choi ◽  
Won Kyu Kwak ◽  
Kyu Sik Cho ◽  
Sung Ki Kim ◽  
Jin Jang

2000 ◽  
Author(s):  
Pi-Fu Chen ◽  
Jr-Hong Chen ◽  
Dou-I Chen ◽  
HsixgJu Sung ◽  
June-Wei Hwang ◽  
...  

1993 ◽  
Vol 297 ◽  
Author(s):  
Byung Chul Ahn ◽  
Jeong Hyun Kim ◽  
Dong Gil Kim ◽  
Byeong Yeon Moon ◽  
Kwang Nam Kim ◽  
...  

The hydrogenation effect was studied in the fabrication of amorphous silicon thin film transistor using APCVD technique. The inverse staggered type a-Si TFTs were fabricated with the deposited a-Si and SiO2 films by the atmospheric pressure (AP) CVD. The field effect mobility of the fabricated a-Si TFT is 0.79 cm2/Vs and threshold voltage is 5.4V after post hydrogenation. These results can be applied to make low cost a-Si TFT array using an in-line APCVD system.


2009 ◽  
Vol 30 (1) ◽  
pp. 36-38 ◽  
Author(s):  
J. H. Oh ◽  
D. H. Kang ◽  
W. H. Park ◽  
J. Jang ◽  
Y. J. Chang ◽  
...  

2007 ◽  
Vol 124-126 ◽  
pp. 259-262
Author(s):  
Jae Hong Jeon ◽  
Kang Woong Lee

We investigated the effect of amorphous silicon pattern design regarding to light induced leakage current in amorphous silicon thin film transistor. In addition to conventional design, where amorphous silicon layer is protruding outside the gate electrode, we designed and fabricated amorphous silicon thin film transistors in another two types of bottom gated structure. The one is that the amorphous silicon layer is located completely inside the gate electrode and the other is that the amorphous silicon layer is protruding outside the gate electrode but covered completely by the source and drain electrode. Measurement of the light induced leakage current caused by backlight revealed that the design where the amorphous silicon is located inside the gate electrode was the most effective however the last design was also effective in reducing the leakage current about one order lower than that of the conventional design.


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