scholarly journals Origin of the Magnetoresistance in Oxide Tunnel Junctions Determined through Electric Polarization Control of the Interface

2015 ◽  
Vol 5 (4) ◽  
Author(s):  
Hisashi Inoue ◽  
Adrian G. Swartz ◽  
Nicholas J. Harmon ◽  
Takashi Tachikawa ◽  
Yasuyuki Hikita ◽  
...  
2019 ◽  
Vol 11 (46) ◽  
pp. 43473-43479 ◽  
Author(s):  
Jiankun Li ◽  
Chen Ge ◽  
Haotian Lu ◽  
Haizhong Guo ◽  
Er-Jia Guo ◽  
...  

2003 ◽  
Vol 93 (10) ◽  
pp. 6423-6425 ◽  
Author(s):  
B. G. Park ◽  
T. D. Lee ◽  
T. H. Lee ◽  
C. G. Kim ◽  
C. O. Kim

2019 ◽  
Vol 125 (20) ◽  
pp. 203104 ◽  
Author(s):  
Henryk Turski ◽  
Shyam Bharadwaj ◽  
Huili (Grace) Xing ◽  
Debdeep Jena

2004 ◽  
Vol 241 (7) ◽  
pp. 1490-1493 ◽  
Author(s):  
J. S. Noh ◽  
C. B. Eom ◽  
M. G. Lagally ◽  
J. Z. Sun ◽  
H. C. Kim

2017 ◽  
Vol 2017 ◽  
pp. 1-8 ◽  
Author(s):  
Dominique Drouin ◽  
Gabriel Droulers ◽  
Marina Labalette ◽  
Bruno Lee Sang ◽  
Patrick Harvey-Collard ◽  
...  

We present a versatile nanodamascene process for the realization of low-power nanoelectronic devices with different oxide junctions. With this process we have fabricated metal/insulator/metal junctions, metallic single electron transistors, silicon tunnel field effect transistors, and planar resistive memories. These devices do exploit one or two nanometric-scale tunnel oxide junctions based on TiO2, SiO2, HfO2, Al2O3, or a combination of those. Because the nanodamascene technology involves processing temperatures lower than 300°C, this technology is fully compatible with CMOS back-end-of-line and is used for monolithic 3D integration.


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