Roll-forward and rollback recovery: performance-reliability trade-off

1997 ◽  
Vol 46 (3) ◽  
pp. 372-378 ◽  
Author(s):  
D.K. Pradhan ◽  
N.H. Vaidya
Materials ◽  
2020 ◽  
Vol 13 (11) ◽  
pp. 2581
Author(s):  
Meng Zhang ◽  
Baikui Li ◽  
Jin Wei

The application of conventional power metal-oxide-semiconductor field-effect transistor (MOSFET) is limited by the famous one-dimensional “silicon limit” (1D-limit) in the trade-off relationship between specific on-resistance (RSP) and breakdown voltage (BV). In this paper, a new power MOSFET architecture is proposed to achieve a beyond-1D-limit RSP-BV trade-off. Numerical TCAD (technology computer-aided design) simulations were carried out to comparatively study the proposed MOSFET, the conventional power MOSFET, and the superjunction MOSFET. All the devices were designed with the same breakdown voltage of ~550 V. The proposed MOSFET features a deep trench between neighboring p-bodies and multiple p-islands located at the sidewall and bottom of the trench. The proposed MOSFET allows a high doping concentration in the drift region, which significantly reduces its RSP compared to the conventional power MOSFET. The multiple p-islands split the electric field into multiple peaks and help the proposed MOSFET maintain a similar breakdown voltage to the conventional power MOSFET with the same drift region thickness. Another famous device technology, the superjunction MOSFET (SJ-MOSFET), also breaks the 1D-limit. However, the SJ-MOSFET suffers a snappy reverse recovery performance, which is a notorious drawback of SJ-MOSFET and limits the range of its application. On the contrary, the proposed MOSFET presents a superior reverse recovery performance and can be used in various power switching applications where hard commutation is required.


1982 ◽  
Vol 14 (2) ◽  
pp. 109-113 ◽  
Author(s):  
Suleyman Tufekci
Keyword(s):  

2012 ◽  
Vol 11 (3) ◽  
pp. 118-126 ◽  
Author(s):  
Olive Emil Wetter ◽  
Jürgen Wegge ◽  
Klaus Jonas ◽  
Klaus-Helmut Schmidt

In most work contexts, several performance goals coexist, and conflicts between them and trade-offs can occur. Our paper is the first to contrast a dual goal for speed and accuracy with a single goal for speed on the same task. The Sternberg paradigm (Experiment 1, n = 57) and the d2 test (Experiment 2, n = 19) were used as performance tasks. Speed measures and errors revealed in both experiments that dual as well as single goals increase performance by enhancing memory scanning. However, the single speed goal triggered a speed-accuracy trade-off, favoring speed over accuracy, whereas this was not the case with the dual goal. In difficult trials, dual goals slowed down scanning processes again so that errors could be prevented. This new finding is particularly relevant for security domains, where both aspects have to be managed simultaneously.


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