Physical mapping and performance study of a multi-clock 3-Dimensional Network-on-Chip mesh

2009 ◽  
Author(s):  
Matt Grange ◽  
Awet Yemane Weldezion ◽  
Dinesh Pamunuwa ◽  
Roshan Weerasekera ◽  
Zhonghai Lu ◽  
...  
Keyword(s):  
Physical Mapping ◽  
Network On Chip ◽  
Performance Study ◽  
3 Dimensional ◽  
Dimensional Network ◽  
And Performance ◽  
On Chip

HETEROGENEOUS 3D NETWORK-ON-CHIP ARCHITECTURES: AREA AND POWER AWARE DESIGN TECHNIQUES

2013 ◽  
Vol 22 (04) ◽  
pp. 1350016 ◽  
Author(s):  
MICHAEL O. AGYEMAN ◽  
ALI AHMADINIA ◽  
ALIREZA SHAHRABI
Keyword(s):  
Three Dimensional ◽  
Network On Chip ◽  
Communication Delays ◽  
Generation System ◽  
Area Efficiency ◽  
Dimensional Network ◽  
3D Network ◽  
Packet Latency ◽  
And Performance ◽  
On Chip

Three-dimensional Network-on-Chip (3D NoC) architectures have gained a lot of popularity to solve the on-chip communication delays of next generation System-on-Chip (SoC) systems. However, the vertical interconnects of 3D NoC are expensive and complex to manufacture. Also, 3D router architecture consumes more power and occupies more area per chip floorplan compared to a 2D router. Hence, more efficient architectures should be designed. In this paper, we propose area efficient and low power 3D heterogeneous NoC architectures, which combines both the power and performance benefits of 2D routers and 3D NoC-bus hybrid router architectures in 3D NoC architectures. Experimental results show a negligible penalty (less than 5%) in average packet latency of the proposed heterogeneous 3D NoC architectures compared to typical homogeneous 3D NoCs, while the heterogeneity provides power and area efficiency of up to 61% and 19.7%, respectively.

A new efficient multi‐task applications mapping for three‐dimensional Network‐on‐Chip based MPSoC

2021 ◽  
Author(s):  
Khadidja Gaffour ◽  
Mohammed Kamel Benhaoua ◽  
Abou El Hassan Benyamina ◽  
Amit Kumar Singh
Keyword(s):  
Three Dimensional ◽  
Network On Chip ◽  
Dimensional Network ◽  
On Chip

scholarly journals Model of Network-on-Chip routers and performance analysis

2011 ◽  
Vol 8 (13) ◽  
pp. 986-993 ◽  
Author(s):  
Youhui Zhang ◽  
Xiaoguo Dong ◽  
Siqing Gan ◽  
Weimin Zheng
Keyword(s):  
Performance Analysis ◽  
Network On Chip ◽  
And Performance ◽  
On Chip
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