A new efficient multi‐task applications mapping for three‐dimensional Network‐on‐Chip based MPSoC

2021 ◽  
Author(s):  
Khadidja Gaffour ◽  
Mohammed Kamel Benhaoua ◽  
Abou El Hassan Benyamina ◽  
Amit Kumar Singh
Keyword(s):  
Three Dimensional ◽  
Network On Chip ◽  
Dimensional Network ◽  
On Chip

HETEROGENEOUS 3D NETWORK-ON-CHIP ARCHITECTURES: AREA AND POWER AWARE DESIGN TECHNIQUES

2013 ◽  
Vol 22 (04) ◽  
pp. 1350016 ◽  
Author(s):  
MICHAEL O. AGYEMAN ◽  
ALI AHMADINIA ◽  
ALIREZA SHAHRABI
Keyword(s):  
Three Dimensional ◽  
Network On Chip ◽  
Communication Delays ◽  
Generation System ◽  
Area Efficiency ◽  
Dimensional Network ◽  
3D Network ◽  
Packet Latency ◽  
And Performance ◽  
On Chip

Three-dimensional Network-on-Chip (3D NoC) architectures have gained a lot of popularity to solve the on-chip communication delays of next generation System-on-Chip (SoC) systems. However, the vertical interconnects of 3D NoC are expensive and complex to manufacture. Also, 3D router architecture consumes more power and occupies more area per chip floorplan compared to a 2D router. Hence, more efficient architectures should be designed. In this paper, we propose area efficient and low power 3D heterogeneous NoC architectures, which combines both the power and performance benefits of 2D routers and 3D NoC-bus hybrid router architectures in 3D NoC architectures. Experimental results show a negligible penalty (less than 5%) in average packet latency of the proposed heterogeneous 3D NoC architectures compared to typical homogeneous 3D NoCs, while the heterogeneity provides power and area efficiency of up to 61% and 19.7%, respectively.

An Efficient Partitioning Algorithm Based on Hypergraph for 3D Network-On-Chip Architecture Floorplanning

2019 ◽  
Vol 28 (05) ◽  
pp. 1950075 ◽  
Author(s):  
Junyan Tan ◽  
Chunhua Cai
Keyword(s):  
Three Dimensional ◽  
Network On Chip ◽  
Three Dimensions ◽  
Layer By Layer ◽  
Task Partitioning ◽  
Silicon Area ◽  
Dimensional Network ◽  
3D Network ◽  
Partitioning Algorithm ◽  
On Chip

Network-on-Chip (NoC) supplies a scalable and fast interconnect for the communication between the different IP cores in the System-on-Chip (SoC). With the growing complexity in consumer embedded systems, the emerging SoC architectures integrate more and more components for the different signal processing tasks. Two dimensional Network-on-Chip (2D NoC) becomes a bottleneck for the development of the SoC architecture because of its limitation on the area of chip and the long latency. In this case, SoC research is forcing on the exploration of three dimensions (3D) technology for developing the next generation of large SoC which integrates three dimensional Network-on-Chip (3D NoC) for the communication architecture. 3D design technology resolves the vertical inter-layer connection issue by Through-Silicon Vias (TSVs). However, TSVs occupy significant silicon area which limits the inter-layer links of the 3D NoC. Therefore, the task partitioning on 3D NoC must be judicious in large SoC design. In this paper, we propose an efficient layer-aware partitioning algorithm based on hypergraph (named ELAP-NoC) for the task partitioning with TSV minimization for 3D NoC architecture floorplanning. ELAP-NoC contains divergence stage and convergence stage. ELAP-NoC supplies firstly a multi-way min-cut partitioning to gradually divide a given design layer by layer in the divergence stage in order to get an initial solution, then this solution is refined in convergence stage. The experiments show that ELAP-NoC performs a better capacity in the partitioning of the different numbers of cores which supplies the first step for the 3D NoC floorplanning.

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