This paper presents an original method of power loss validation in medium-voltage SiC MOSFET (metal–oxide–semiconductor field-effect transistor) modules of a three-phase inverter. The base of this method is a correct description of the on-state performance of the diodes and the transistors in a PWM (pulse width modulation)-controlled inverter phase leg. Combined electro-thermal calculations are applied to precisely estimate the losses in the power devices and then, to find the suitable circuit parameters of a test circuit to emulate these conditions. A simple square-wave-controlled half-bridge with an inductive load enables the electrical and thermal stresses comparable to these in the inverter, and moreover, provided equations that confirmed the possibility of balancing the load between the diodes and the transistors. The circuit with 3.3 kV SiC MOSFETs was tested to verify the impact of selected parameters on power losses with the main focus on duty ratio. The same module was applied, in addition to an inductive load (3 × 112 μH) and two sets of DC-link capacitors (750 μF), to validate a phase leg of a 220 kVA inverter. In spite of a significantly apparent power, the active power delivered from the DC supply settled around 1 kW, which was enough to emulate 390 W of losses in two transistors and diodes.
Four-Level Three-Phase Inverter With Reduced Component Count for Low and Medium Voltage Applications