Wireless sensor networks are used in many diverse application scenarios that
require the network designer to trade off different factors. Two such factors of importance
in many wireless sensor networks are communication reliability and battery
life. This paper describes an efficient, low complexity, high throughput channel
decoder suited to decoding low-density parity-check (LDPC) codes. LDPC
codes have demonstrated excellent error-correcting ability such that a number of
recent wireless standards have opted for their inclusion. Hardware realisation of
practical LDPC decoders is a challenging area especially when power efficient solutions
are needed. Implementation details are given for an LDPC decoding algorithm,
termed adaptive threshold bit flipping (ATBF), designed for low complexity
and low power operation. The ATBF decoder was implemented in 90 nm CMOS at
0.9 V using a standard cell design flow and was shown to operate at 250 MHz achieving
a throughput of 252 Gb/s/iteration. The decoder area was 0.72 mm2 with a power
consumption of 33.14 mW and a very small energy/decoded bit figure of 1.3 pJ.
A Reliability Profile Based Low-Complexity Dynamic Schedule LDPC Decoding
