Toward High Accuracy Transaction Level Energy Modeling for System-on-Chip Buses

2011 ◽  
Author(s):  
Shengnan Xu ◽  
Yangdong Deng
Keyword(s):  
High Accuracy ◽  
System On Chip ◽  
Energy Modeling ◽  
Level Energy ◽  
Transaction Level ◽  
On Chip

scholarly journals SystemC Transaction-Level Modeling of an MPSoC Platform Based on an Open Source ISS by Using Interprocess Communication

2008 ◽  
Vol 2008 ◽  
pp. 1-10
Author(s):  
Sami Boukhechem ◽  
El-Bay Bourennane
Keyword(s):  
Open Source ◽  
System On Chip ◽  
Open Architecture ◽  
Multiprocessor System ◽  
Instruction Set ◽  
Levels Of Abstraction ◽  
Transaction Level Modeling ◽  
Synthesis Tool ◽  
Transaction Level ◽  
On Chip

Transaction-level modeling (TLM) is a promising technique to deal with the increasing complexity of modern embedded systems. This model allows a system designer to model a complete application, composed of hardware and software parts, at several levels of abstraction. For this purpose, we use systemC, which is proposed as a standardized modeling language. This paper presents a transaction-level modeling cosimulation methodology for modeling, validating, and verifying our embedded open architecture platform. The proposed platform is an open source multiprocessor system-on-chip (MPSoC) platform, integrated under the synthesis tool for adaptive and reconfigurable system-on-chip (STARSoC) environment. It relies on the integration between an open source instruction set simulators (ISSs), OR1Ksim platform, and the systemC simulation environment which contains other components (wishbone bus, memories, , etc.). The aim of this work is to provide designers with the possibility of faster and efficient architecture exploration at a higher level of abstractions, starting from an algorithmic description to implementation details.

scholarly journals iDocChip: A Configurable Hardware Architecture for Historical Document Image Processing

2021 ◽  
Author(s):  
Menbere Kina Tekleyohannes ◽  
Vladimir Rybalkin ◽  
Muhammad Mohsin Ghaffar ◽  
Javier Alejandro Varela ◽  
Norbert Wehn ◽  
...  
Keyword(s):  
Power Consumption ◽  
Character Recognition ◽  
Optical Character Recognition ◽  
High Accuracy ◽  
Document Image ◽  
System On Chip ◽  
Historical Documents ◽  
Optical Character ◽  
Historical Archives ◽  
On Chip

AbstractIn recent years, $$\hbox {optical character recognition (OCR)}$$ optical character recognition (OCR) systems have been used to digitally preserve historical archives. To transcribe historical archives into a machine-readable form, first, the documents are scanned, then an $$\hbox {OCR}$$ OCR is applied. In order to digitize documents without the need to remove them from where they are archived, it is valuable to have a portable device that combines scanning and $$\hbox {OCR}$$ OCR capabilities. Nowadays, there exist many commercial and open-source document digitization techniques, which are optimized for contemporary documents. However, they fail to give sufficient text recognition accuracy for transcribing historical documents due to the severe quality degradation of such documents. On the contrary, the anyOCR system, which is designed to mainly digitize historical documents, provides high accuracy. However, this comes at a cost of high computational complexity resulting in long runtime and high power consumption. To tackle these challenges, we propose a low power energy-efficient accelerator with real-time capabilities called iDocChip, which is a configurable hybrid hardware-software programmable $$\hbox {System-on-Chip (SoC)}$$ System-on-Chip (SoC) based on anyOCR for digitizing historical documents. In this paper, we focus on one of the most crucial processing steps in the anyOCR system: Text and Image Segmentation, which makes use of a multi-resolution morphology-based algorithm. Moreover, an optimized $$\hbox {FPGA}$$ FPGA -based hybrid architecture of this anyOCR step along with its optimized software implementations are presented. We demonstrate our results on multiple embedded and general-purpose platforms with respect to runtime and power consumption. The resulting hardware accelerator outperforms the existing anyOCR by 6.2$$\times$$ × , while achieving 207$$\times$$ × higher energy-efficiency and maintaining its high accuracy.

scholarly journals NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor

Sensors ◽  
2020 ◽  
Vol 20 (4) ◽  
pp. 1069 ◽  
Author(s):  
Tomasz Borejko ◽  
Krzysztof Marcinek ◽  
Krzysztof Siwiec ◽  
Paweł Narczyk ◽  
Adam Borkowski ◽  
...  
Keyword(s):  
Global Navigation Satellite System ◽  
Satellite System ◽  
High Accuracy ◽  
System On Chip ◽  
Navigation Satellite ◽  
Dual Frequency ◽  
Gnss Receiver ◽  
On Chip ◽  
Application Processor ◽  
Global Navigation Satellite

A dual-frequency all-in-one Global Navigation Satellite System (GNSS) receiver with a multi-core 32-bit RISC (reduced instruction set computing) application processor was integrated and manufactured as a System-on-Chip (SoC) in a 110 nm CMOS (complementary metal-oxide semiconductor) process. The GNSS RF (radio frequency) front-end with baseband navigation engine is able to receive, simultaneously, Galileo (European Global Satellite Navigation System) E1/E5ab, GPS (US Global Positioning System) L1/L1C/L5, BeiDou (Chinese Navigation Satellite System) B1/B2, GLONASS (GLObal NAvigation Satellite System of Russian Government) L1/L3/L5, QZSS (Quasi-Zenith Satellite System development by the Japanese government) L1/L5 and IRNSS (Indian Regional Navigation Satellite System) L5, as well as all SBAS (Satellite Based Augmentation System) signals. The ability of the GNSS to detect such a broad range of signals allows for high-accuracy positioning. The whole SoC (system-on-chip), which is connected to a small passive antenna, provides precise position, velocity and time or raw GNSS data for hybridization with the IMU (inertial measurement unit) without the need for an external application processor. Additionally, user application can be executed directly in the SoC. It works in the −40 to +105 °C temperature range with a 1.5 V supply. The assembled test-chip takes 100 pins in a QFN (quad-flat no-leads) package and needs only a quartz crystal for the on-chip reference clock driver and optional SAW (surface acoustic wave) filters. The radio performance for both wideband (52 MHz) channels centered at L1/E1 and L5/E5 is NF = 2.3 dB, G = 131 dB, with 121 dBc/Hz of phase noise @ 1 MHz offset from the carrier, consumes 35 mW and occupies a 4.5 mm2 silicon area. The SoC reported in the paper is the first ever dual-frequency single-chip GNSS receiver equipped with a multi-core application microcontroller integrated with embedded flash memory for the user application program.

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