Reliability Enhancement for Multi-level Cell NAND Flash Memory Using Error Asymmetry

2019 ◽  
Author(s):  
Duc-Phuc Nguyen ◽  
Khoa Le Trung ◽  
Fakhreddine Ghaffari ◽  
David Declercq
Keyword(s):  
Flash Memory ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Multi Level ◽  
Reliability Enhancement

A 56-nm CMOS 99-${\hbox {mm}}^{2} $ 8-Gb Multi-Level NAND Flash Memory With 10-MB/s Program Throughput

2007 ◽  
Vol 42 (1) ◽  
pp. 219-232 ◽  
Author(s):  
Ken Takeuchi ◽  
Yasushi Kameda ◽  
Susumu Fujimura ◽  
Hiroyuki Otake ◽  
Koji Hosono ◽  
...  
Keyword(s):  
Flash Memory ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Multi Level

Implications of the Logical Decode on the Radiation Response of a Multi-Level Cell NAND Flash Memory

2013 ◽  
Vol 60 (6) ◽  
pp. 4451-4456 ◽  
Author(s):  
J. David Ingalls ◽  
Matthew J. Gadlage ◽  
Adam R. Duncan ◽  
Matthew J. Kay ◽  
Patrick L. Cole ◽  
...  
Keyword(s):  
Flash Memory ◽  
Radiation Response ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Multi Level

Effect of Word-Line Bias on Linearity of Multi-Level Conductance Steps for Multi-Layer Neural Networks Based on NAND Flash Cells

2020 ◽  
Vol 20 (7) ◽  
pp. 4138-4142
Author(s):  
Sung-Tae Lee ◽  
Suhwan Lim ◽  
Nagyong Choi ◽  
Jong-Ho Bae ◽  
Dongseok Kwon ◽  
...  
Keyword(s):  
Neural Networks ◽  
Flash Memory ◽  
Storage Capacity ◽  
High Density ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Data Set ◽  
Source Line ◽  
In Series ◽  
Multi Level

NAND flash memory which is mature technology has great advantage in high density and great storage capacity per chip because cells are connected in series between a bit-line and a source-line. Therefore, NAND flash cell can be used as a synaptic device which is very useful for a high-density synaptic array. In this paper, the effect of the word-line bias on the linearity of multi-level conductance steps of the NAND flash cell is investigated. A 3-layer perceptron network (784×200×10) is trained by a suitable weight update method for NAND flash memory using MNIST data set. The linearity of multi-level conductance steps is improved as the word line bias increases from Vth −0.5 to Vth +1 at a fixed bit-line bias of 0.2 V. As a result, the learning accuracy is improved as the word-line bias increases from Vth −0.5 to Vth+1.

Channel-stacked NAND flash memory with layer selection by multi-level operation (LSM)

2013 ◽  
Author(s):  
Wandong Kim ◽  
Joo Yun Seo ◽  
Yoon Kim ◽  
Se Hwan Park ◽  
Sang Ho Lee ◽  
...  
Keyword(s):  
Flash Memory ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Multi Level
Sign in / Sign up

Export Citation Format

Share Document