A reconfigurable 4-GS/s power-efficient floating-point FFT processor design and implementation based on single-sided binary-tree decomposition

Integration ◽  
2019 ◽  
Vol 66 ◽  
pp. 164-172
Author(s):  
Xing Wei ◽  
Haigang Yang ◽  
Wei Li ◽  
Zhihong Huang ◽  
Tao Yin ◽  
...  
Keyword(s):  
Binary Tree ◽  
Tree Decomposition ◽  
Floating Point ◽  
Processor Design ◽  
Power Efficient ◽  
Design And Implementation ◽  
Fft Processor

scholarly journals Double Precision Floating Point Fft Processor using Vedic Mathematics

2019 ◽  
Vol 8 (4) ◽  
pp. 8533-8538
Keyword(s):  
Fourier Transform ◽  
Fast Fourier Transform ◽  
Floating Point ◽  
Double Precision ◽  
Power Efficient ◽  
Vedic Mathematics ◽  
Communication Signal ◽  
Fft Processor ◽  
Complex Multiplications ◽  
Point Fast Fourier Transform

There should be rapid, efficient and simple process for every scenario now a day. To compute the N point DFT, Fast Fourier Transform (FFT) is a productive algorithm. It has great applications in communication, signal and image processing and instrumentation. In the implementation of FFT one of the challenges is the complex multiplications, so to make this process rapid and simple it’s necessary for a multiplier to be fast and power efficient. To tackle this problem Karatsuba sutra and Nikhilam sutra are an efficient method of multiplication in Vedic Mathematics. This paper will present a design methodology of Double Precision Floating Point Fast Fourier Transform (FFT) Processor.The execution time and complexity can be reduced by the algorithm which is there in Vedic.The main aim is to make FFT Processor process rapid and simple by designing a multiplier which is fast and power efficient by using double precision floating point and Vedic Mathematics concepts.

Design and implementation of a GaAs systolic floating-point processing element

1996 ◽  
Vol 143 (5) ◽  
pp. 325
Author(s):  
A. Beaumont-Smith ◽  
W. Marwood ◽  
C.C. Lim ◽  
K. Eshraghian
Keyword(s):  
Processing Element ◽  
Floating Point ◽  
Design And Implementation

Design of area and power efficient Radix-4 DIT FFT butterfly unit using floating point fused arithmetic

2016 ◽  
Vol 23 (7) ◽  
pp. 1669-1681 ◽  
Author(s):  
E. Prabhu ◽  
H. Mangalam ◽  
S. Karthick
Keyword(s):  
Floating Point ◽  
Power Efficient

scholarly journals Design and Implementation of a Ultra-High-Speed Pipelined FFT Processor

1985 ◽  
Vol 21 (7) ◽  
pp. 725-732
Author(s):  
Michitaka KAMEYAMA ◽  
Tatsuo HIGUCHI ◽  
Junichi KONNO ◽  
Kaoru TAKASUKA
Keyword(s):  
High Speed ◽  
Design And Implementation ◽  
Fft Processor ◽  
Ultra High Speed
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