Stack memory implementation and analysis of timing constraint, power and memory using FPGA

Author(s):  
Vandana Thind ◽  
Nisha Pandey ◽  
Bishwajeet Pandey ◽  
D M Akbar Hussain
Keyword(s):  
Energies ◽  
2021 ◽  
Vol 14 (11) ◽  
pp. 3322
Author(s):  
Sara Alonso ◽  
Jesús Lázaro ◽  
Jaime Jiménez ◽  
Unai Bidarte ◽  
Leire Muguira

Smart grid endpoints need to use two environments within a processing system (PS), one with a Linux-type operating system (OS) using the Arm Cortex-A53 cores for management tasks, and the other with a standalone execution or a real-time OS using the Arm Cortex-R5 cores. The Xen hypervisor and the OpenAMP framework allow this, but they may introduce a delay in the system, and some messages in the smart grid need a latency lower than 3 ms. In this paper, the Linux thread latencies are characterized by the Cyclictest tool. It is shown that when Xen hypervisor is used, this scenario is not suitable for the smart grid as it does not meet the 3 ms timing constraint. Then, standalone execution as the real-time part is evaluated, measuring the delay to handle an interrupt created in programmable logic (PL). The standalone application was run in A53 and R5 cores, with Xen hypervisor and OpenAMP framework. These scenarios all met the 3 ms constraint. The main contribution of the present work is the detailed characterization of each real-time execution, in order to facilitate selecting the most suitable one for each application.


2006 ◽  
Vol 2 (1) ◽  
pp. 1-5 ◽  
Author(s):  
Yoon-Seok Jeong ◽  
Tae-Wan Kim ◽  
Sun-Young Han ◽  
Chun-Hyon Chang

2017 ◽  
Vol 28 (9) ◽  
pp. 2567-2580 ◽  
Author(s):  
Weiwen Jiang ◽  
Edwin Hsing-Mean Sha ◽  
Xianzhang Chen ◽  
Lei Yang ◽  
Lei Zhou ◽  
...  

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