A Multiple Faults Test Generation Algorithm Based on Neural Networks and Chaotic Searching for Digital Circuits

2010 ◽  
Author(s):  
Ying Zhao ◽  
Yanjuan Li
Keyword(s):  
Neural Networks ◽  
Test Generation ◽  
Digital Circuits ◽  
Generation Algorithm ◽  
Multiple Faults ◽  
Chaotic Searching

scholarly journals Temporal Logic Based Hierarchical Test Generation for Sequential VLSI Circuits

VLSI Design ◽  
1994 ◽  
Vol 2 (1) ◽  
pp. 69-80 ◽  
Author(s):  
Anand V. Hudli ◽  
Raghu V. Hudli
Keyword(s):  
Temporal Logic ◽  
Test Generation ◽  
Digital Circuits ◽  
Difficult Problem ◽  
Sequential Circuits ◽  
Vlsi Circuits ◽  
Temporal Behavior ◽  
Generation Algorithm

Test generation for sequential VLSI circuits has remained a difficult problem to solve. The difficulty arises because of reasoning about temporal behavior of sequential circuits. We use temporal logic to model digital circuits. Temporal Logic can model circuits hierarchically. A set of heuristics is given to aid during test generation. A hierarchical test generation algorithm is proposed.

Low Power and High Speed Sequential Circuits Test Architecture

2019 ◽  
Vol 12 ◽  
Author(s):  
Ahmed K. Jameil ◽  
Yasir Amer Abbas ◽  
Saad Al-Azawi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Test Generation ◽  
High Speed ◽  
Fir Filter ◽  
Sequential Circuits ◽  
Fir Filters ◽  
Design Verification ◽  
Sequential Circuit ◽  
Generation Algorithm

Background: The designed circuits are tested for faults detection in fabrication to determine which devices are defective. The design verification is performed to ensure that the circuit performs the required functions after manufacturing. Design verification is regarded as a test form in both sequential and combinational circuits. The analysis of sequential circuits test is more difficult than in the combinational circuit test. However, algorithms can be used to test any type of sequential circuit regardless of its composition. An important sequential circuit is the finite impulse response (FIR) filters that are widely used in digital signal processing applications. Objective: This paper presented a new design under test (DUT) algorithm for 4-and 8-tap FIR filters. Also, the FIR filter and the proposed DUT algorithm is implemented using field programmable gate arrays (FPGA). Method: The proposed test generation algorithm is implemented in VHDL using Xilinx ISE V14.5 design suite and verified by simulation. The test generation algorithm used FIR filtering redundant faults to obtain a set of target faults for DUT. The fault simulation is used in DUT to assess the benefit of test pattern in fault coverage. Results: The proposed technique provides average reductions of 20 % and 38.8 % in time delay with 57.39 % and 75 % reductions in power consumption and 28.89 % and 28.89 % slices reductions for 4- and 8-tap FIR filter, respectively compared to similar techniques. Conclusions: The results of implementation proved that a high speed and low power consumption design can be achieved. Further, the speed of the proposed architecture is faster than that of existing techniques.

Fourier Neural Networks and Generalized Single Hidden Layer Networks in Aircraft Engine Fault Diagnostics

2005 ◽  
Vol 128 (4) ◽  
pp. 773-782 ◽  
Author(s):  
H. S. Tan
Keyword(s):  
Neural Network ◽  
Neural Networks ◽  
Network Architecture ◽  
Fourier Transforms ◽  
Aircraft Engine ◽  
Fault Classification ◽  
Noise Robustness ◽  
Fault Diagnostics ◽  
Multiple Faults ◽  
Hidden Layer

The conventional approach to neural network-based aircraft engine fault diagnostics has been mainly via multilayer feed-forward systems with sigmoidal hidden neurons trained by back propagation as well as radial basis function networks. In this paper, we explore two novel approaches to the fault-classification problem using (i) Fourier neural networks, which synthesizes the approximation capability of multidimensional Fourier transforms and gradient-descent learning, and (ii) a class of generalized single hidden layer networks (GSLN), which self-structures via Gram-Schmidt orthonormalization. Using a simulation program for the F404 engine, we generate steady-state engine parameters corresponding to a set of combined two-module deficiencies and require various neural networks to classify the multiple faults. We show that, compared to the conventional network architecture, the Fourier neural network exhibits stronger noise robustness and the GSLNs converge at a much superior speed.

The First Computational Theory of Cognition

2020 ◽  
pp. 107-127
Author(s):  
Gualtiero Piccinini
Keyword(s):  
Neural Networks ◽  
Body Problem ◽  
Digital Circuits ◽  
Finite Automata ◽  
Cognitive Activity ◽  
Logic Gates ◽  
Computer Design ◽  
Computational Theory ◽  
Modern Computer ◽  
The Mind

McCulloch and Pitts were the first to use and Alan Turing’s notion of computation to understand neural, and thus cognitive, activity. McCulloch and Pitts’s contributions included (i) a formalism whose refinement and generalization led to the notion of finite automata, which is an important formalism in computability theory, (ii) a technique that inspired the notion of logic design, which is a fundamental part of modern computer design, (iii) the first use of computation to address the mind–body problem, and (iv) the first modern computational theory of cognition, which posits that neurons are equivalent to logic gates and neural networks are digital circuits.

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