A new IEEE 1149.1 boundary scan design for the detection of delay defects

Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537) ◽

10.1109/date.2000.840311 ◽

2002 ◽

Author(s):

Sungju Park ◽

Taehyung Kim

Keyword(s):

Boundary Scan ◽

Scan Design ◽

Ieee 1149.1 ◽

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A new IEEE 1149.1 boundary scan design for the detection of delay defects

Proceedings of the conference on Design, automation and test in Europe - DATE '00 ◽

10.1145/343647.343822 ◽

2000 ◽

Author(s):

Sungju Park ◽

Taehyung Kim

Keyword(s):

Boundary Scan ◽

Scan Design ◽

Ieee 1149.1 ◽

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A user programmable macrocell generator for the IEEE 1149.1 boundary scan standard interface port

Microprocessing and Microprogramming ◽

10.1016/0165-6074(92)90359-f ◽

1992 ◽

Vol 35 (1-5) ◽

pp. 493-500

Author(s):

Mark Royals ◽

Tassos Markas ◽

Nick Kanopoulos

Keyword(s):

Boundary Scan ◽

Standard Interface ◽

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A chip to embedded system test process using IEEE 1149.1 boundary scan

Proceedings of ELECTRO '94 ◽

10.1109/electr.1994.472652 ◽

2002 ◽

Author(s):

J.E. Kadaras

Keyword(s):

Embedded System ◽

Boundary Scan ◽

Ieee 1149.1 ◽

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Manufacturing defects testing of a multi-chip-module using IEEE 1149.1 boundary scan test and embedded built-in test software

AUTOTESTCON 93 ◽

10.1109/autest.1993.396355 ◽

2002 ◽

Author(s):

B.J. Round

Keyword(s):

Boundary Scan ◽

Manufacturing Defects ◽

Scan Test ◽

Ieee 1149.1 ◽

Boundary Scan Test

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Optimal placement of IEEE 1149.1 test port and boundary scan resources for wafer scale integration

Proceedings. International Test Conference 1990 ◽

10.1109/test.1990.114009 ◽

2002 ◽

Author(s):

D.L. Landis ◽

P. Singh

Keyword(s):

Optimal Placement ◽

Boundary Scan ◽

Wafer Scale ◽

Wafer Scale Integration ◽

Ieee 1149.1 ◽

Scale Integration

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Boundary-scan design for cost-sensitive applications

Microprocessors and Microsystems ◽

10.1016/0141-9331(93)90004-q ◽

1993 ◽

Vol 17 (5) ◽

pp. 277-280

Author(s):

Peter Harrod

Keyword(s):

Boundary Scan ◽

Scan Design ◽

Design For Cost

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The Current Status and Prospect in Boundary Scan Design

Journal of The Japan Institute of Electronics Packaging ◽

10.5104/jiep.24.96 ◽

2021 ◽

Vol 24 (1) ◽

pp. 96-98

Keyword(s):

Current Status ◽

Boundary Scan ◽

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Boundary scan design and verification flow using buffer chain method

AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360) ◽

10.1109/apasic.1999.824089 ◽

2003 ◽

Author(s):

Eun-Seok Chae ◽

Hong-Shin Jun ◽

Hye-Kyong Song

Keyword(s):

Boundary Scan ◽

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Low cost boundary scan controller for didactic applications (IEEE 1149.1)

2015 3rd Experiment International Conference (exp.at'15) ◽

10.1109/expat.2015.7463266 ◽

2015 ◽

Author(s):

Andre Fidalgo ◽

Andre Couto ◽

Manuel Felgueiras ◽

Gustavo Alves

Keyword(s):

Low Cost ◽

Boundary Scan ◽

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IS IEEE 1149.1 BOUNDARY SCAN COST EFFECTIVE: A SIMPLE CASE STUDY

Proceedings International Test Conference 1992 ◽

10.1109/test.1992.527810 ◽

2005 ◽

Author(s):

B. Caldwell ◽

T. Langford

Keyword(s):

Cost Effective ◽

Boundary Scan ◽

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