Built-in Self-Test and Fault Localization for Inter-Layer Vias in Monolithic 3D ICs

Monolithic 3D (M3D) integration provides massive vertical integration through the use of nanoscale inter-layer vias (ILVs). However, high integration density and aggressive scaling of the inter-layer dielectric make ILVs especially prone to defects. We present a low-cost built-in self-test (BIST) method that requires only two test patterns to detect opens, stuck-at faults, and bridging faults (shorts) in ILVs. We also propose an extended BIST architecture for fault detection, called Dual-BIST, to guarantee zero ILV fault masking due to single BIST faults and negligible ILV fault masking due to multiple BIST faults. We analyze the impact of coupling between adjacent ILVs arranged in a 1D array in block-level partitioned designs. Based on this analysis, we present a novel test architecture called Shared-BIST with the added functionality of localizing single and multiple faults, including coupling-induced faults. We introduce a systematic clustering-based method for designing and integrating a delay bank with the Shared-BIST architecture for testing small-delay defects in ILVs with minimal yield loss. Simulation results for four two-tier M3D benchmark designs highlight the effectiveness of the proposed BIST framework.

Small Delay Tracing Defect Testing

This Small Delay Tracing Defect Testing detect small delay defects by creating internal signal races. The races are created by launching transitions along simultaneous two paths, a reference path and a test path. The arrival times of the transitions on a ‘convergence’ or common gate determine the result of the race. On the output of the convergence gate, a static hazard created by a small delay defect presence on the test path which is directed to the input of a scan-latch. A glitch detector is added to the scan latch which records the presence or absence of the glitch.

Full-Order Sliding Mode Observer Based on Synchronous Frequency Tracking Filter for High-Speed Interior PMSM Sensorless Drives

In the research of the high-speed sensorless control strategy of an interior permanent-magnet synchronous motor (IPMSM), considering the harmonic influence of inverter nonlinearity on traditional sliding mode observer method, a full-order sliding mode observer (SMO) method based on synchronous frequency tracking filtering is proposed. This method avoids the phase delay defects caused by the use of filters in traditional second-order SMO. Then, the observed extended electromotive force (EMF) signal is filtered using a synchronous frequency tracking (SFT) function. It tracks the changing stator current and filters out harmonics that are not part of the tracking signal to achieve static tracking of the stator current. Then, the rotor speed can be estimated by a Luenberger-based observer. Experimental results verify the effectiveness and feasibility of the proposed method.

X-Sand Filter: An X-Tolerant Response Compaction Technique for Faster-Than-At-Speed Testing

Faster-than-at-speed testing provides an effective way of detecting small delay defects but at the cost of increased number of unknown logic values on longer paths of the circuit under test. For efficient testing, these unknown logic values need to be filtered out of the circuit under test output. In past, different compaction hardware schemes were presented to minimize these unknown logic values, all these schemes were effective in handling a limited number of unknown values arising due to design imperfections, processing problems manufacturing problems material problems etc. but no effective compaction scheme is available to handle large number of these logic values arising due to faster-than-at-speed testing. This paper presents “X-sand filter”, a compaction technique, an extension of already presented idea of “X-tolerant signature analysis”. Here, the idea of “X-tolerant signature analysis” with modifications has been applied and has attained a considerable improvement in the X-tolerance. X-sand filter is a hierarchical structure that handles gradual X-density reduction in an efficient manner. Simulation results obtained show that we can achieve up to 90 % reduction in the X-density if we use X-sand filter. Extensions to the work of X-sand filter can be carried out in future to enhance its capabilities and make its configuration more flexible in terms of layer designing.

X-Sand Filter: An X-Tolerant Response Compaction Technique for Faster-Than-At-Speed Testing

Faster-than-at-speed testing provides an effective way of detecting small delay defects but at the cost of increased number of unknown logic values on longer paths of the circuit under test. For efficient testing, these unknown logic values need to be filtered out of the circuit under test output. In past, different compaction hardware schemes were presented to minimize these unknown logic values, all these schemes were effective in handling a limited number of unknown values arising due to design imperfections, processing problems manufacturing problems material problems etc. but no effective compaction scheme is available to handle large number of these logic values arising due to faster-than-at-speed testing. This paper presents “X-sand filter”, a compaction technique, an extension of already presented idea of “X-tolerant signature analysis”. Here, the idea of “X-tolerant signature analysis” with modifications has been applied and has attained a considerable improvement in the X-tolerance. X-sand filter is a hierarchical structure that handles gradual X-density reduction in an efficient manner. Simulation results obtained show that we can achieve up to 90 % reduction in the X-density if we use X-sand filter. Extensions to the work of X-sand filter can be carried out in future to enhance its capabilities and make its configuration more flexible in terms of layer designing.