Proceedings of the conference on Design, automation and test in Europe - DATE '00

Multi-node static logic implications for redundancy identification

Proceedings of the conference on Design, automation and test in Europe - DATE '00 ◽

10.1145/343647.344102 ◽

2000 ◽

Cited By ~ 2

Author(s):

Kabir Gulrajani ◽

Michael S. Hsiao

Keyword(s):

Redundancy Identification ◽

Static Logic

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The generalized boundary curve --- a common method for automatic nominal design centering of analog circuits

Proceedings of the conference on Design, automation and test in Europe - DATE '00 ◽

10.1145/343647.343695 ◽

2000 ◽

Cited By ~ 4

Author(s):

R. Schwencker ◽

F. Schenkel ◽

H. Graeb ◽

K. Antreich

Keyword(s):

Analog Circuits ◽

Boundary Curve ◽

Common Method ◽

Design Centering

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Compact modeling of nonlinear distortion in analog communication circuits

Proceedings of the conference on Design, automation and test in Europe - DATE '00 ◽

10.1145/343647.343795 ◽

2000 ◽

Cited By ~ 15

Author(s):

Piet Wambacq ◽

Petr Dobrovolný ◽

Stéphane Donnay ◽

Marc Engles ◽

Ivo Bolsens

Keyword(s):

Nonlinear Distortion ◽

Compact Modeling ◽

Communication Circuits ◽

Analog Communication

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Automatic test bench generation for validation of RT-level descriptions

Proceedings of the conference on Design, automation and test in Europe - DATE '00 ◽

10.1145/343647.343802 ◽

2000 ◽

Cited By ~ 10

Author(s):

F. Corno ◽

M. Sonza Reorda ◽

G. Squillero ◽

A. Manzone ◽

A. Pincetti

Keyword(s):

Test Bench ◽

Automatic Test

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System synthesis for multiprocessor embedded applications

Proceedings of the conference on Design, automation and test in Europe - DATE '00 ◽

10.1145/343647.343897 ◽

2000 ◽

Cited By ~ 3

Author(s):

Luigi Carro ◽

Márcio Kreutz ◽

Flávio R. Wagner ◽

Márcio Oyamada

Keyword(s):

System Synthesis ◽

Embedded Applications

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Automatic equivalence check of circuit descriptions at clocked algorithmic and register transfer level (poster paper)

Proceedings of the conference on Design, automation and test in Europe - DATE '00 ◽

10.1145/343647.344347 ◽

2000 ◽

Author(s):

Jens Schönberr ◽

Bernd Straube

Keyword(s):

Register Transfer Level ◽

Register Transfer ◽

Poster Paper ◽

Equivalence Check

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Predicting coupled noise in RC circuits

Proceedings of the conference on Design, automation and test in Europe - DATE '00 ◽

10.1145/343647.343836 ◽

2000 ◽

Author(s):

Bernard N. Sheehan

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Exploiting hierarchy for multiple error correction in combinational circuits (poster paper)

Proceedings of the conference on Design, automation and test in Europe - DATE '00 ◽

10.1145/343647.344346 ◽

2000 ◽

Cited By ~ 1

Author(s):

Dirk W. Hoffman ◽

Thomas Kropf

Keyword(s):

Error Correction ◽

Combinational Circuits ◽

Poster Paper ◽

Multiple Error

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Efficient power co-estimation techniques for system-on-chip design

Proceedings of the conference on Design, automation and test in Europe - DATE '00 ◽

10.1145/343647.343691 ◽

2000 ◽

Cited By ~ 6

Author(s):

Marcello Lajolo ◽

Anand Raghunathan ◽

Sujit Dey

Keyword(s):

System On Chip ◽

Chip Design ◽

Estimation Techniques ◽

On Chip ◽

Efficient Power

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All digital built-in delay and crosstalk measurement for on-chip buses

Proceedings of the conference on Design, automation and test in Europe - DATE '00 ◽

10.1145/343647.343841 ◽

2000 ◽

Cited By ~ 4

Author(s):

Chauchin Su ◽

Yue-Tsang Chen ◽

Mu-Jeng Huang ◽

Gen-Nan Chen ◽

Chung-Len Lee

Keyword(s):

On Chip

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Proceedings of the conference on Design, automation and test in Europe - DATE '00
Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By ACM Press

Multi-node static logic implications for redundancy identification

The generalized boundary curve --- a common method for automatic nominal design centering of analog circuits

Compact modeling of nonlinear distortion in analog communication circuits

Automatic test bench generation for validation of RT-level descriptions

System synthesis for multiprocessor embedded applications

Automatic equivalence check of circuit descriptions at clocked algorithmic and register transfer level (poster paper)

Predicting coupled noise in RC circuits

Exploiting hierarchy for multiple error correction in combinational circuits (poster paper)

Efficient power co-estimation techniques for system-on-chip design

All digital built-in delay and crosstalk measurement for on-chip buses

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Proceedings of the conference on Design, automation and test in Europe - DATE '00Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By ACM Press

Multi-node static logic implications for redundancy identification

The generalized boundary curve --- a common method for automatic nominal design centering of analog circuits

Compact modeling of nonlinear distortion in analog communication circuits

Automatic test bench generation for validation of RT-level descriptions

System synthesis for multiprocessor embedded applications

Automatic equivalence check of circuit descriptions at clocked algorithmic and register transfer level (poster paper)

Predicting coupled noise in RC circuits

Exploiting hierarchy for multiple error correction in combinational circuits (poster paper)

Efficient power co-estimation techniques for system-on-chip design

All digital built-in delay and crosstalk measurement for on-chip buses

Proceedings of the conference on Design, automation and test in Europe - DATE '00
Latest Publications