A study of estimation of balance degree using CMRR mesurement for power distribution interconnection on printed circuit board

Author(s):  
Mutsumi Shimazaki ◽  
Hideki Asai
Author(s):  
Hansang Lim ◽  
Do-Hwan Jung ◽  
Geono Kwon ◽  
Young Jong Lee ◽  
Jun Seo Park

An automotive junction box distributes electric power to electric systems installed in a vehicle with overcurrent protection. As a larger number of electric systems are installed, the junction box is equipped with more components, functionalities and connections. However, owing to the fuse accessibility, its installation space is so restricted that a downsized design is required for the junction box. The junction box is composed of small signal circuitry for control and monitoring, and large current-carrying circuitry for power distribution which includes many parallel traces. Because of these unique features, widely used techniques for downsizing printed-circuit boards are not applicable. Also, there is no rule for designing large current-carrying parallel traces, and it is difficult to optimize the size of the printed-circuit board for the automotive junction box. This paper presents the design rules for a printed-circuit board when downsizing a junction box. First, the layout strategy for the power distribution components is presented, which is determined by the sum of the squares of the currents flowing through connector pairs. Then, the thermal effects of parallel traces are simulated for different conditions by using thermal analysis software. Based on the results, an analytical estimation of the additional temperature rises due to parallel traces and rules for a thermally effective arrangement of the parallel traces are presented.


Author(s):  
Albert Chee W. Lu ◽  
Wei Fan ◽  
Lai L. Wai ◽  
Toshiro Yamazaki ◽  
Jacinto Jun Jarcia ◽  
...  

This paper describes a design optimization of power distribution networks using embedded passive technology. A frequency-domain methodology was used to study the impedance characteristics of printed circuit board power planes with embedded decoupling capacitors, and also the interaction with discrete capacitors, package structures and on-chip capacitors. Two different thin-core materials were analyzed. Key aspects of power distribution networks including plane spreading inductance, plane pair via inductance and transfer impedance were also analyzed. Utilizing broadband PDN models, extracted with full-wave EM techniques to account for frequency-dependent behaviour, frequency-domain SPICE simulations were carried out to determine the system impedance characteristics at multiple port locations up to 2 GHz. The frequency-domain analysis shows that in bare boards, significant SSN interaction between different port locations within the printed circuit board is present. It is concluded that the proper use of high-K distributed capacitors at optimal locations on the printed circuit board helps to alleviate SSN interaction between different port locations. Several multi-layer test vehicles have been fabricated and characterized, with good correlation between simulation results and measured values.


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