A 2.2mW, Continuous-Time Sigma-Delta ADC for Voice Coding with 95dB Dynamic Range in a 65nm CMOS Process

2006 ◽  
Author(s):  
Lukas Dorrer ◽  
Franz Kuttner ◽  
Andreas Santner ◽  
Claus Kropf ◽  
Thomas Hartig ◽  
...  
Keyword(s):  
Continuous Time ◽  
Dynamic Range ◽  
Cmos Process ◽  
Sigma Delta ◽  
Sigma Delta Adc

VCO-BASED CONTINUOUS-TIME SIGMA DELTA ADC BASED ON A DUAL-VCO-QUANTIZER-LOOP STRUCTURE

2013 ◽  
Vol 22 (09) ◽  
pp. 1340013 ◽  
Author(s):  
Z. T. XU ◽  
X. L. ZHANG ◽  
J. Z. CHEN ◽  
S. G. HU ◽  
Q. YU ◽  
...  
Keyword(s):  
Continuous Time ◽  
Signal To Noise Ratio ◽  
Quantization Noise ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Loop Structure ◽  
Signal To Noise ◽  
Sigma Delta ◽  
Analog To Digital ◽  
Sigma Delta Adc

This paper explores a continuous time (CT) sigma delta (ΣΔ) analog-to-digital converter (ADC) based on a dual-voltage-controlled oscillator (VCO)-quantizer-loop structure. A third-order filter is adopted to reduce quantization noise and VCO nonlinearity. Even-order harmonics of VCO are significantly reduced by the proposed dual-VCO-quantizer-loop structure. The prototype with 10 MHz bandwidth and 400 MHz clock rate is designed using a 0.18 μm RF CMOS process. Simulation results show that the signal-to-noise ratio and signal-to-noise distortion ratio (SNDR) are 76.9 and 76 dB, respectively, consuming 37 mA at 1.8 V. The key module of the ADC, which is a 4-bit VCO-based quantizer, can convert the voltage signal into a frequency signal and quantize the corresponding frequency to thermometer codes at 400 MS/s.

A 20-mW 640-MHz CMOS Continuous-Time $\Sigma\Delta$ ADC With 20-MHz Signal Bandwidth, 80-dB Dynamic Range and 12-bit ENOB

2006 ◽  
Vol 41 (12) ◽  
pp. 2641-2649 ◽  
Author(s):  
Gerhard Mitteregger ◽  
Christian Ebner ◽  
Stephan Mechnig ◽  
Thomas Blon ◽  
Christophe Holuigue ◽  
...  
Keyword(s):  
Continuous Time ◽  
Dynamic Range ◽  
Sigma Delta ◽  
Sigma Delta Adc

Adaptive Blocker Rejection Continuous-Time $\Sigma \Delta $ ADC for Mobile WiMAX Applications

2009 ◽  
Vol 44 (10) ◽  
pp. 2766-2779 ◽  
Author(s):  
Hyungseok Kim ◽  
Junghan Lee ◽  
Tino Copani ◽  
Seyfi Bazarjani ◽  
Sayfe Kiaei ◽  
...  
Keyword(s):  
Continuous Time ◽  
Mobile Wimax ◽  
Sigma Delta ◽  
Sigma Delta Adc

An Extended-Counting Incremental Sigma–Delta ADC with Hardware-Reuse Technique

2016 ◽  
Vol 25 (05) ◽  
pp. 1650038
Author(s):  
Xinji Zeng ◽  
Jing Gao ◽  
Liu Yang ◽  
Jiangtao Xu
Keyword(s):  
Conversion Rate ◽  
Cmos Process ◽  
Digital Output ◽  
Sigma Delta ◽  
Design And Implementation ◽  
Conversion Time ◽  
Cyclic Adc ◽  
Sigma Delta Adc ◽  
Oversampling Ratio ◽  
Least Significant Bits

This paper presents the design and implementation of an extended-counting incremental sigma–delta ADC (IDC) with hardware-reuse technique. The proposed ADC architecture is a cascaded configuration of a second-order IDC and a two-stage cyclic ADC. The operation of the ADC consists of the “coarse phase” and the “fine phase”. In the “coarse phase”, the circuit works as an IDC to achieve the most significant bits (MSBs) and produce the residue voltage. Then in the “fine phase”, it is reused and changed to work as a cyclic ADC to quantize the residue voltage and achieve the least significant bits (LSBs). Eventual digital output is achieved by combining the two parts together. The utilization of extended-counting technique significantly reduces the conversion time and increases the conversion rate, and the hardware-reuse technique removes the demand for additional circuit area. The ADC is designed in 0.5[Formula: see text][Formula: see text]m CMOS process, which has a conversion rate of 43.48[Formula: see text]kS/s with oversampling ratio (OSR) of 23 and achieves 84.83[Formula: see text]dB SNDR and 13.799-bit ENOB. It consumes 2.4[Formula: see text]mW with a 5[Formula: see text]V voltage supply, and the FOM is 3.87[Formula: see text]pJ/step.

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