Multi-Bit Sigma Delta ADC with Reduced Feedback Levels, Extended Dynamic Range and Increased Tolerance for Analog Imperfections

This paper proposes using a fractional-order digital loop integrator to improve the robust stability of Sigma-Delta modulator, thus extending the integer-order Sigma-Delta modulator to a non-integer-order (fractional-order) one in the Sigma-Delta ADC design field. The proposed fractional-order Sigma-Delta modulator has reasonable noise characteristics, dynamic range, and bandwidth; moreover the signal-to-noise ratio (SNR) is improved remarkably. In particular, a 2nd-order digital loop integrator and a digital PIλDμ controller are combined to work as the fractional-order digital loop integrator, which is realized using FPGA; this will reduce the ASIC analog circuit layout design and chip testing difficulties. The parameters of the proposed fractional-order Sigma-Delta modulator are tuned by using swarm intelligent algorithm, which offers opportunity to simplify the process of tuning parameters and further improve the noise performance. Simulation results are given and they demonstrate the efficiency of the proposed fractional-order Sigma-Delta modulator.

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A High-Dynamic-Range Switched-Capacitor Sigma-Delta ADC for Digital Micromechanical Vibration Gyroscopes

Micromachines ◽

10.3390/mi9080372 ◽

2018 ◽

Vol 9 (8) ◽

pp. 372 ◽

Cited By ~ 5

Author(s):

Risheng Lv ◽

Weiping Chen ◽

Xiaowei Liu

Keyword(s):

Dynamic Range ◽

Signal To Noise Ratio ◽

High Dynamic Range ◽

Cmos Technology ◽

Noise Cancellation ◽

Switched Capacitor ◽

Noise Shaping ◽

Sigma Delta ◽

Multi Stage ◽

Sigma Delta Adc

This paper presents a multi-stage noise shaping (MASH) switched-capacitor (SC) sigma-delta (ΣΔ) analog-to-digital converter (ADC) composed of an analog modulator with an on-chip noise cancellation logic and a reconfigurable digital decimator for MEMS digital gyroscope applications. A MASH 2-1-1 structure is employed to guarantee an absolutely stable modulation system. Based on the over-sampling and noise-shaping techniques, the core modulator architecture is a cascade of three single-loop stages containing feedback paths for systematic optimization to avoid deterioration in conversion accuracy caused by capacitor mismatch. A digital noise cancellation logic is also included to eliminate residual quantization errors in the former two stages, and those in the last stage are shaped by a fourth-order modulation. A multi-rate decimator follows the analog modulator to suit variable gyroscope bandwidth. Manufactured in a standard 0.35 μm CMOS technology, the whole chip occupies an area of 3.8 mm2. Experimental results show a maximum signal-to-noise ratio (SNR) of 100.2 dB and an overall dynamic range (DR) of 107.6 dB, with a power consumption of 3.2 mW from a 5 V supply. This corresponds to a state-of-the-art figure-of-merit (FoM) of 165.6 dB.

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A 2.2mW, Continuous-Time Sigma-Delta ADC for Voice Coding with 95dB Dynamic Range in a 65nm CMOS Process

2006 Proceedings of the 32nd European Solid-State Circuits Conference ◽

10.1109/esscir.2006.307564 ◽

2006 ◽

Cited By ~ 10

Author(s):

Lukas Dorrer ◽

Franz Kuttner ◽

Andreas Santner ◽

Claus Kropf ◽

Thomas Hartig ◽

...

Keyword(s):

Continuous Time ◽

Dynamic Range ◽

Cmos Process ◽

Sigma Delta ◽

Sigma Delta Adc

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A 0.58 mm2 CMOS reconfigurable sigma delta ADC for mobile WiMAX receiver

Ingenieria y Universidad ◽

10.11144/javeriana.iyu23-1.crsd ◽

2019 ◽

Vol 23 (1) ◽

Author(s):

Jihene Mallek ◽

Houda Daoud ◽

Rahma Aloulou ◽

Hassene Mnif ◽

Mourad Loulou

Keyword(s):

Dynamic Range ◽

Pole Placement ◽

Mobile Wimax ◽

Sigma Delta ◽

Analog To Digital ◽

Placement Method ◽

Channel Bandwidth ◽

Sigma Delta Adc ◽

Multi Mode ◽

Channel Bandwidths

Objective: In this work the design of a fourth-order Reconfigurable Sigma Delta analog-to-digital converter (ΣΔ ADC) for 5MHz, 7MHz or 10MHz channel bandwidths are presented. Materials and methods: Our design technique aims to keep the same ADC architecture in response to multi-band and multi-mode aspects of Mobile WiMAX standard. To this end, we set each sampling frequency corresponding to each channel bandwidth, in order that the same OSR value would be kept for the different channel bandwidths. This technique is intended to optimize the power and area of the ADC that efficiently covers varying channel bandwidths. Moreover, we use the pole placement method to calculate the optimized filter coefficients of Continuous-Time Sigma-Delta (CT ΣΔ) ADC. Results and discussion: Over 5MHz, 7MHz and 10MHz channel bandwidths, the ADC achieved 72.89dB, 67.26dB and 66.47dB peak SNR values, respectively and a dynamic range of 73.5dB, 69.47dB and 66.5dB respectively with only 28mW, 28.2mW and 28.6mW power consumption respectively. Conclusions: The design of the proposed reconfigurable ADC intended for use in the mobile WiMAX standard were achieved. Moreover, the results obtained are satisfactory and are in accordance with theoretical expectations.

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