A 22 mW 512 MHz CMOS continuous time sigma delta ADC in 1.2 V with 16 MHz signal bandwidth and 70 dB dynamic range

2012 ◽  
Vol 72 (1) ◽  
pp. 47-53 ◽  
Author(s):  
Jun Yuan ◽  
Yintang Yang
2006 ◽  
Vol 41 (12) ◽  
pp. 2641-2649 ◽  
Author(s):  
Gerhard Mitteregger ◽  
Christian Ebner ◽  
Stephan Mechnig ◽  
Thomas Blon ◽  
Christophe Holuigue ◽  
...  

2009 ◽  
Vol 44 (10) ◽  
pp. 2766-2779 ◽  
Author(s):  
Hyungseok Kim ◽  
Junghan Lee ◽  
Tino Copani ◽  
Seyfi Bazarjani ◽  
Sayfe Kiaei ◽  
...  

2013 ◽  
Vol 22 (09) ◽  
pp. 1340013 ◽  
Author(s):  
Z. T. XU ◽  
X. L. ZHANG ◽  
J. Z. CHEN ◽  
S. G. HU ◽  
Q. YU ◽  
...  

This paper explores a continuous time (CT) sigma delta (ΣΔ) analog-to-digital converter (ADC) based on a dual-voltage-controlled oscillator (VCO)-quantizer-loop structure. A third-order filter is adopted to reduce quantization noise and VCO nonlinearity. Even-order harmonics of VCO are significantly reduced by the proposed dual-VCO-quantizer-loop structure. The prototype with 10 MHz bandwidth and 400 MHz clock rate is designed using a 0.18 μm RF CMOS process. Simulation results show that the signal-to-noise ratio and signal-to-noise distortion ratio (SNDR) are 76.9 and 76 dB, respectively, consuming 37 mA at 1.8 V. The key module of the ADC, which is a 4-bit VCO-based quantizer, can convert the voltage signal into a frequency signal and quantize the corresponding frequency to thermometer codes at 400 MS/s.


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