On scan path design for stuck-open and delay fault detection

Proceedings ETC 93 Third European Test Conference ◽

10.1109/etc.1993.246553 ◽

2002 ◽

Author(s):

J. Leenstra ◽

M. Koch ◽

T. Schwederski

Keyword(s):

Fault Detection ◽

Delay Fault ◽

Path Design ◽

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Arrangement of latches in scan-path design to improve delay fault coverage

Proceedings. International Test Conference 1990 ◽

10.1109/test.1990.114046 ◽

2002 ◽

Author(s):

W. Mao ◽

M.D. Ciletti

Keyword(s):

Fault Coverage ◽

Delay Fault ◽

Path Design ◽

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Correlation-reduced scan-path design to improve delay fault coverage

Proceedings of the 28th conference on ACM/IEEE design automation conference - DAC '91 ◽

10.1145/127601.127631 ◽

1991 ◽

Author(s):

Weiwei Mao ◽

Michael D. Ciletti

Keyword(s):

Fault Coverage ◽

Delay Fault ◽

Path Design ◽

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The Economics of Scan-Path Design for Testability

Economics of Electronic Design, Manufacture and Test ◽

10.1007/978-1-4757-5048-5_5 ◽

1994 ◽

pp. 53-67 ◽

Author(s):

Prab Varma ◽

Tushar Gheewala

Keyword(s):

Design For Testability ◽

Path Design ◽

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Augmenting scan path SRLs with an XOR network to enhance delay fault testing

IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems DFTVS-94 ◽

10.1109/dftvs.1994.630014 ◽

2002 ◽

Author(s):

Zaifu Zhang ◽

R.D. McLeod ◽

W. Pedrycz

Keyword(s):

Fault Testing ◽

Delay Fault ◽

Delay Fault Testing ◽

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Incremental computation of delay fault detection probability for variation-aware test generation

2014 19th IEEE European Test Symposium (ETS) ◽

10.1109/ets.2014.6847805 ◽

2014 ◽

Author(s):

Marcus Wagner ◽

Hans-Joachim Wunderlich

Keyword(s):

Fault Detection ◽

Test Generation ◽

Detection Probability ◽

Delay Fault ◽

Incremental Computation

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Scan Design with Shadow Flip-flops for Low Performance Overhead and Concurrent Delay Fault Detection

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013 ◽

10.7873/date.2013.227 ◽

2013 ◽

Author(s):

Sebastien Sarrazin ◽

Samuel Evain ◽

Lirida Alves de Barros Naviner ◽

Yannick Bonhomme ◽

Valentin Gherman

Keyword(s):

Fault Detection ◽

Scan Design ◽

Delay Fault ◽

Low Performance

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Cost-free scan: a low-overhead scan path design

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.720320 ◽

1998 ◽

Vol 17 (9) ◽

pp. 852-861 ◽

Author(s):

Chih-Chang Lin ◽

M. Marek-Sadowska ◽

M.T.-C. Lee ◽

Kuang-Chien Chen

Keyword(s):

Path Design ◽

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A scalable scan-path test point insertion technique to enhance delay fault coverage for standard scan designs

International Test Conference, 2003. Proceedings. ITC 2003. ◽

10.1109/test.2003.1270884 ◽

2004 ◽

Author(s):

Seongmoon Wang ◽

S.T. Chakradhar

Keyword(s):

Fault Coverage ◽

Insertion Technique ◽

Delay Fault ◽

Test Point Insertion ◽

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Reducing correlation to improve coverage of delay faults in scan-path design

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.277638 ◽

1994 ◽

Vol 13 (5) ◽

pp. 638-646 ◽

Author(s):

Weiwei Mao ◽

M.D. Ciletti

Keyword(s):

Delay Faults ◽

Path Design ◽

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SIC-TPG for path delay fault detection in VLSI circuits using scan insertion method

2021 Devices for Integrated Circuit (DevIC) ◽

10.1109/devic50843.2021.9455859 ◽

2021 ◽

Author(s):

Sabir Hussain ◽

M A Raheem ◽

Afaq Ahmed

Keyword(s):

Fault Detection ◽

Vlsi Circuits ◽

Delay Fault ◽

Insertion Method ◽

Path Delay Fault

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