Small analog-to-digital converter (ADCs) are very popular when they are required in many interfaces or system designs. Ever since the system-on-chip (SOC) became one of the major trends in chip designs, the demand for small and less power draining ADCs has urgently emerged. The area factor is particularly critical when it comes to the cost issue. In this paper, a small but stable ADC intellectual property (IP) macro design is proposed wherein a binary search scheme is utilized to produce the ADC function. A total of eight cycles are needed to convert the analog signal based upon simulation results. A physical chip is fabricated to verify the correctness of our design.
On-chip reduced-code static linearity test of $V_{cm}$ -based switching SAR ADCs using an incremental analog-to-digital converter
