SYNTEST: an environment for system-level design for test

Proceedings EURO-DAC '92: European Design Automation Conference ◽

10.1109/eurdac.1992.246212 ◽

2003 ◽

Author(s):

H. Harmanani ◽

C. Papachristou ◽

S. Chiu ◽

M. Nourani

Keyword(s):

System Level ◽

Design For Test ◽

System Level Design ◽

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System-Level Design for Test of Fully Differential Analog Circuits

32nd Design Automation Conference ◽

10.1109/dac.1995.249989 ◽

1995 ◽

Author(s):

Bapiraju Vinnakota

Keyword(s):

Analog Circuits ◽

System Level ◽

Design For Test ◽

System Level Design ◽

Fully Differential ◽

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System-level design for test of fully differential analog circuits

Proceedings of the 32nd ACM/IEEE conference on Design automation conference - DAC '95 ◽

10.1145/217474.217569 ◽

1995 ◽

Author(s):

Bapiraju Vinnakota ◽

Ramesh Harjani ◽

Nicholas J. Stessman

Keyword(s):

Analog Circuits ◽

System Level ◽

Design For Test ◽

System Level Design ◽

Fully Differential ◽

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System-level design for test of fully differential analog circuits

IEEE Journal of Solid-State Circuits ◽

10.1109/4.540065 ◽

1996 ◽

Vol 31 (10) ◽

pp. 1526-1534 ◽

Author(s):

N.J. Stessman ◽

B. Vinnakota ◽

R. Harjani

Keyword(s):

Analog Circuits ◽

System Level ◽

Design For Test ◽

System Level Design ◽

Fully Differential ◽

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An Approach to System-level Design for Test

System-level Test and Validation of Hardware/Software Systems - Springer Series in Advanced Microelectronics ◽

10.1007/1-84628-145-8_8 ◽

2005 ◽

pp. 121-149

Author(s):

G. Jervan ◽

R. Ubar ◽

Z. Peng ◽

P. Eles

Keyword(s):

System Level ◽

Design For Test ◽

System Level Design ◽

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MPSoC System Level Design Method Based on Universal Interconnect Network

Journal of Computer-Aided Design & Computer Graphics ◽

10.3724/sp.j.1089.2010.10721 ◽

2010 ◽

Vol 22 (5) ◽

pp. 858-864

Author(s):

Yuanshen Li ◽

Yun Pan ◽

Yong Ding ◽

Xiaolang Yan

Keyword(s):

Design Method ◽

System Level ◽

System Level Design ◽

Level Design ◽

Interconnect Network

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A system-level design method for RF receiver front-end with low power consumption

Analog Integrated Circuits and Signal Processing ◽

10.1007/s10470-021-01879-y ◽

2021 ◽

Author(s):

Ziba Fazel ◽

Mojtaba Atarodi ◽

Sirus Sadughi

Keyword(s):

Power Consumption ◽

Low Power ◽

Design Method ◽

System Level ◽

Low Power Consumption ◽

System Level Design ◽

Rf Receiver ◽

Front End ◽

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Low-complexity SPICE Analog Behavioral Modeling of the ideal battery for system level design

2020 IEEE ANDESCON ◽

10.1109/andescon50619.2020.9272055 ◽

2020 ◽

Author(s):

Ariel Jimenez ◽

Natalia Morales ◽

Carlos Paez ◽

Arturo Fajardo ◽

Gabriel Perilla

Keyword(s):

Low Complexity ◽

Behavioral Modeling ◽

System Level ◽

System Level Design ◽

Level Design ◽

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A Case Study of FPGA Blokus Duo Solver by System-Level Design

ACM SIGARCH Computer Architecture News ◽

10.1145/2693714.2693725 ◽

2014 ◽

Vol 42 (4) ◽

pp. 57-62

Author(s):

Yuki Ando ◽

Masataka Ogawa ◽

Yuya Mizoguchi ◽

Kouta Kumagai ◽

Miaw Torng-Der ◽

...

Keyword(s):

System Level ◽

System Level Design ◽

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Innovative system-level design environment based on FORM for transport processing system

Proceedings Design, Automation and Test in Europe ◽

10.1109/date.1998.655962 ◽

2002 ◽

Author(s):

K. Higuchi ◽

K. Shirakawa

Keyword(s):

Processing System ◽

System Level ◽

System Level Design ◽

Design Environment ◽

Innovative System ◽

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A component library for IP core based system level design automation

2006 7th International Conference on Computer-Aided Industrial Design and Conceptual Design ◽

10.1109/caidcd.2006.329370 ◽

2006 ◽

Author(s):

Chenqian Jiang ◽

Jinian Bian ◽

Kang Zhao ◽

Kun Tong

Keyword(s):

Design Automation ◽

System Level ◽

System Level Design ◽

Ip Core ◽

Component Library ◽

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