FPGA implementation of template matching using binary sum of absolute difference

Author(s):  
Aditya Rachman Putra ◽  
Fadhil Mochammad ◽  
Hans Herdian

Template matching forms the basis of many image processing algorithms and hence the computer vision algorithms. There are many existing template matching algorithms like Sum of Absolute Difference (SAD), Normalized SAD (NSAD), Correlation methods (CORR), Normalized CORR(NCORR), Sum of Squared Difference (SSD), and Normalized SSD(NSSD). In general, as image requires more memory space for storage and much time for processing. The above said methods involves much computation. In any processing, efficiency constraints include many factors, especially accuracy of the results and speed of processing. An approach to reduce the execution time is always most appreciated. As a result of this, a novel method of partial NCC (PNCC) template matching technique is proposed in this paper. A block window approach is used to reduce the number of operations and hence to speed up the processing. A comparative study between existing NCC algorithm and the proposed partial NCC, PNCC algorithm is done. It is experimented and results proves that the execution time is reduced by 8 - 47 times approximately based on the various template images for different main images in PNCC. The accuracy of the result obtained is 100%. This proposed algorithm works for various types of images. The experiment is repeated for various sizes of templates and different sizes of main image. Further improvement in the speed of execution can be achieved by implementation of the proposed algorithm using parallel processors. It may find its importance in the real time image processing


2013 ◽  
Vol 5 (1) ◽  
pp. 36-41
Author(s):  
R. Ganesh ◽  
◽  
Ch. Sandeep Reddy ◽  

Author(s):  
Jeniffer A ◽  
Haripasath S ◽  
Chinthamani S ◽  
Chitra G ◽  
Karthiga V

2019 ◽  
Vol 12 (1) ◽  
pp. 1 ◽  
Author(s):  
Badr El Kari ◽  
Hassan Ayad ◽  
Abdeljalil El Kari ◽  
Mostafa Mjahed ◽  
Claudiu Pozna

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