Multi-input multi-output (MIMO) systems combined
with orthogonal frequency-division multiplexing (OFDM)
gained a wide popularity in wireless applications due to the
potential of providing increased channel capacity and robustness
against multipath fading channels. However these advantages
come at the cost of a very high processing complexity and
the efficient implementation of MIMO-OFDM receivers is today
a major research topic. In this paper, efficient architectures
are proposed for the hardware implementation of the main
building blocks of a MIMO-OFDM receiver. A sphere decoder
architecture flexible to different modulation without any loss in
BER performance is presented while the proposed matrix factorization
implementation allows to achieve the highest throughput
specified in the IEEE 802.11n standard. Finally a novel sphere
decoder approach is presented, which allows for the realization of
new golden space time trellis coded modulation (GST-TCM)
scheme. Implementation cost and offered throughput are provided
for the proposed architectures synthesized on a 0.13 CMOS
standard cell technology or on advanced FPGA devices.
Enabling VLSI Processing Blocks for MIMO-OFDM Communications