Fixed-value impulse noise suppression for images using PDE based Adaptive Two-Stage Median Filter

2011 ◽  
Author(s):  
P Shanmugavadivu ◽  
P S Eliahim Jeevaraj
Keyword(s):  
Impulse Noise ◽  
Noise Suppression ◽  
Median Filter ◽  
Two Stage

scholarly journals Execution of Median Filter Built on FPGA for Trimming Noise Meeting the Real Time Requirements

2019 ◽  
Vol 8 (4) ◽  
pp. 7855-7858
Keyword(s):  
Real Time ◽  
Impulse Noise ◽  
Noise Suppression ◽  
Median Filter ◽  
Sliding Window ◽  
Spatial Filter ◽  
Effective Technique ◽  
The Real ◽  
Time Requirements ◽  
Suppression Process

As images plays a vital in all aspects, there is a need to met the real time requirements in processing the image. Major challenges raised in processing the image is noise. The utmost typical difficult is effective denoising creation as well as quick functioning in the processing of digital image noise suppression process for the need of real time consequences to afford image with high quality this project was introduced. Generally filters plays a major role to remove the impulse noise in acquired images. The filter named sliding window spatial filter which is familiar as median filter is effective technique to eradicate impulse noise from the devoleped image. But in real time, it is very difficult to execute. To overcome this, FPGA methodology is introduced to fulfills the support besides the optimization of major constraints like area, speed, power. In addition to this, it assures technical sustenance of eradicating noise in image as per requirements in real time. Regarding the design and structure appearances in FPGA, Xilinx software is used for simulation and code has been written in Verilog language.

Impulse Noise Suppression Method by Median Filtering with Parity Extraction

2013 ◽  
Vol 846-847 ◽  
pp. 991-994
Author(s):  
Zhen Xing Li
Keyword(s):  
Impulse Noise ◽  
Noise Suppression ◽  
Median Filter ◽  
Window Size ◽  
New Method ◽  
Median Filtering ◽  
Experiment Data ◽  
Simulation And Experiment ◽  
Suppression Method

A new impulse noise suppression method by median filtering with parity extraction was proposed in this paper. The window size of the median filter has important effect on the performance of the filtering result, larger window size can suppress impulse noise effectively but often at cost of loss of the detail information of the signal, while smaller window size can protect the detail information better but results in degrading of the noise suppression. Parity extraction is done to the signal at first and median filtering carries on the odd and even part respectively, and then a new method of median filtering with short window size to suppress the impulse noise is obtained. Simulation and experiment data of telemetry process results show the effectiveness of the proposed method.

FPGA-Based Re-Configurable Architecture for Window-Based Image Processing

2018 ◽  
pp. 273-310
Author(s):  
Kamarujjaman Sk ◽  
Manali Mukherjee ◽  
Mausumi Maitra
Keyword(s):  
Adaptive Filtering ◽  
Impulse Noise ◽  
Noise Suppression ◽  
Digital Images ◽  
Median Filter ◽  
Hardware Architecture ◽  
Efficient Design ◽  
Filtering Method ◽  
Switching Median Filter ◽  
Noise Density

In this proposed book chapter, a simple but efficient presentation of Median Filter, Switching Median Filter, Adaptive Median Filter and Decision-Based Adaptive Filtering Method and their hardware architecture for FPGA is described for removal of up to 99% impulse noise from Digital Images. For hardware architecture, simulation is done using Xilinx ISE 14.5 software of XILINX. For implementation, these approaches utilize Genesys VIRTEX V FPGA device of XC5VLX50T device family. In this approach, we proposed an efficient design for suppression of impulse noise from digital images corrupted by up to 99% impulse noise using decision based adaptive filtering method as well as preserve the details of image. The method works in two different stages – noise detection using switching technique and finally noise suppression and restoration. Experimental results show that our method perform better in terms of PSNR below 80% noise density but above 80% noise density it is almost comparable with the latest methods.

FPGA-Based Re-Configurable Architecture for Window-Based Image Processing

2017 ◽  
pp. 1-46
Author(s):  
Kamarujjaman Sk ◽  
Manali Mukherjee ◽  
Mausumi Maitra
Keyword(s):  
Adaptive Filtering ◽  
Impulse Noise ◽  
Noise Suppression ◽  
Digital Images ◽  
Median Filter ◽  
Hardware Architecture ◽  
Efficient Design ◽  
Filtering Method ◽  
Switching Median Filter ◽  
Noise Density

In this proposed book chapter, a simple but efficient presentation of Median Filter, Switching Median Filter, Adaptive Median Filter and Decision-Based Adaptive Filtering Method and their hardware architecture for FPGA is described for removal of up to 99% impulse noise from Digital Images. For hardware architecture, simulation is done using Xilinx ISE 14.5 software of XILINX. For implementation, these approaches utilize Genesys VIRTEX V FPGA device of XC5VLX50T device family. In this approach, we proposed an efficient design for suppression of impulse noise from digital images corrupted by up to 99% impulse noise using decision based adaptive filtering method as well as preserve the details of image. The method works in two different stages – noise detection using switching technique and finally noise suppression and restoration. Experimental results show that our method perform better in terms of PSNR below 80% noise density but above 80% noise density it is almost comparable with the latest methods.

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