Design and Implementation of 2Bit Vedic Multiplier at 16nm Using PTL Logic

2018 Fourth International Conference on Computing Communication Control and Automation (ICCUBEA) ◽

10.1109/iccubea.2018.8697753 ◽

2018 ◽

Author(s):

Kshitij Sharma ◽

Anubhav Garg ◽

Deepak Agrawal ◽

Anu Mehra ◽

Smita Singhal

Keyword(s):

Design And Implementation ◽

Vedic Multiplier

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An efficient design and implementation of Vedic multiplier in quantum-dot cellular automata

Telecommunication Systems ◽

10.1007/s11235-020-00669-7 ◽

2020 ◽

Vol 74 (4) ◽

pp. 487-496

Author(s):

B. Naresh Kumar Reddy ◽

B. Veena Vani ◽

G. Bhavya Lahari

Keyword(s):

Cellular Automata ◽

Quantum Dot ◽

Efficient Design ◽

Quantum Dot Cellular Automata ◽

Design And Implementation ◽

Vedic Multiplier

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Design and Implementation of a delay and area efficient 32x32bit Vedic Multiplier using Brent Kung Adder

International Journal of Engineering Trends and Technology ◽

10.14445/22315381/ijett-v41p271 ◽

2016 ◽

Vol 41 (8) ◽

pp. 393-398

Author(s):

Ayushi Sharma ◽

◽

Ajit Singh

Keyword(s):

Design And Implementation ◽

Vedic Multiplier ◽

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Design and implementation of energy efficient vedic multiplier using FPGA

2015 International Conference on Information Processing (ICIP) ◽

10.1109/infop.2015.7489379 ◽

2015 ◽

Author(s):

Hemangi P. Patil ◽

S. D. Sawant

Keyword(s):

Energy Efficient ◽

Design And Implementation ◽

Vedic Multiplier

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Design and Implementation of 8-Bit Vedic Multiplier Using CMOS Logic

2013 International Conference on Machine Intelligence and Research Advancement ◽

10.1109/icmira.2013.71 ◽

2013 ◽

Author(s):

Yeshwant Deodhe ◽

Sandeep Kakde ◽

Rushikesh Deshmukh

Keyword(s):

Design And Implementation ◽

Vedic Multiplier

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Design and Implementation of Vedic Multiplier using Compressors

International Journal of Engineering Research and ◽

10.17577/ijertv4is060321 ◽

2015 ◽

Vol V4 (06) ◽

Author(s):

Harish Kumar ◽

HEMANTH KUMAR A R ◽

Keyword(s):

Design And Implementation ◽

Vedic Multiplier

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Design and Implementation of High Speed 16x16 CMOS Vedic Multiplier

International Journal of Electrical Electronics and Computers ◽

10.22161/eec.3.3.2 ◽

2018 ◽

Vol 3 (3) ◽

pp. 7-11

Author(s):

Praveen Kumar Sharma ◽

Gajendra Sujediya

Keyword(s):

Design And Implementation ◽

Vedic Multiplier

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Design and Implementation of FPGA based 64-bit MAC Unit using VEDIC Multiplier and Reversible Logic Gates

Indian Journal of Science and Technology ◽

10.17485/ijst/2017/v10i3/109413 ◽

2017 ◽

Vol 10 (3) ◽

Author(s):

P. SivaNagendra Reddy ◽

M. Saraswathi

Keyword(s):

Logic Gates ◽

Reversible Logic ◽

Design And Implementation ◽

Vedic Multiplier ◽

Reversible Logic Gates

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Design and Implementation of Efficient Vedic Multiplier Using Reversible Logic

Progress in VLSI Design and Test - Lecture Notes in Computer Science ◽

10.1007/978-3-642-31494-0_45 ◽

2012 ◽

pp. 364-366 ◽

Author(s):

P. Saravanan ◽

P. Chandrasekar ◽

Livya Chandran ◽

Nikilla Sriram ◽

P. Kalpana

Keyword(s):

Reversible Logic ◽

Design And Implementation ◽

Vedic Multiplier

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Design and Implementation of a Low Power Vedic Multiplier

International Journal for Research in Applied Science and Engineering Technology ◽

10.22214/ijraset.2018.4686 ◽

2018 ◽

Vol 6 (4) ◽

pp. 4156-4162 ◽

Author(s):

Neethu Johny

Keyword(s):

Low Power ◽

Design And Implementation ◽

Vedic Multiplier

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Modified High Speed 32-bit Vedic Multiplier Design and Implementation

2020 International Conference on Electronics and Sustainable Communication Systems (ICESC) ◽

10.1109/icesc48915.2020.9155882 ◽

2020 ◽

Author(s):

M. Bala Murugesh ◽

S. Nagaraj ◽

J. Jayasree ◽

G. Vijay Kumar Reddy

Keyword(s):

Design And Implementation ◽

Vedic Multiplier

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