Design and Implementation of Efficient Vedic Multiplier Using Reversible Logic

Progress in VLSI Design and Test - Lecture Notes in Computer Science ◽

10.1007/978-3-642-31494-0_45 ◽

2012 ◽

pp. 364-366 ◽

Author(s):

P. Saravanan ◽

P. Chandrasekar ◽

Livya Chandran ◽

Nikilla Sriram ◽

P. Kalpana

Keyword(s):

Reversible Logic ◽

Design And Implementation ◽

Vedic Multiplier

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Design and Implementation of FPGA based 64-bit MAC Unit using VEDIC Multiplier and Reversible Logic Gates

Indian Journal of Science and Technology ◽

10.17485/ijst/2017/v10i3/109413 ◽

2017 ◽

Vol 10 (3) ◽

Author(s):

P. SivaNagendra Reddy ◽

M. Saraswathi

Keyword(s):

Logic Gates ◽

Reversible Logic ◽

Design And Implementation ◽

Vedic Multiplier ◽

Reversible Logic Gates

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Design and Implementation of Efficient RGB to Gray scale Converter Architectures Using Reversible Logic

2020 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER) ◽

10.1109/discover50404.2020.9278066 ◽

2020 ◽

Author(s):

Swathi. U ◽

Smitha. U

Keyword(s):

Reversible Logic ◽

Design And Implementation

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Design and implementation of H/W efficient Multiplier: Reversible logic gate approach

2015 International Conference on Communications and Signal Processing (ICCSP) ◽

10.1109/iccsp.2015.7322800 ◽

2015 ◽

Author(s):

K. Babulu ◽

M. Kamaraju ◽

P. Bujjibabu ◽

K. Pradeep

Keyword(s):

Reversible Logic ◽

Design And Implementation

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Design and Implementation of 8 Bit Shift Register using Reversible Logic

2018 International Conference on Current Trends towards Converging Technologies (ICCTCT) ◽

10.1109/icctct.2018.8551165 ◽

2018 ◽

Author(s):

M. Rajeshwari ◽

Rohini. S. Hongal ◽

Rajashekar. B. Shettar

Keyword(s):

Reversible Logic ◽

Shift Register ◽

Design And Implementation

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Design and FPGA Implementation of High Performance 8-BIT Vedic Multiplier Using Reversible Logic Based Barrel Shifter

Proceedings of Second International Conference on Signal Processing, Image Processing and VLSI ◽

10.3850/978-981-09-6200-5_vlsi-74 ◽

2015 ◽

Author(s):

Abhilasha . ◽

Sudharshan . ◽

S.L. Anusha

Keyword(s):

High Performance ◽

Reversible Logic ◽

Fpga Implementation ◽

Vedic Multiplier ◽

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Design and Implementation of Reversible Logic Based Ternary Content Addressable Memory

Smart Intelligent Computing and Applications - Smart Innovation, Systems and Technologies ◽

10.1007/978-981-32-9690-9_42 ◽

2019 ◽

pp. 405-413

Author(s):

C. Santhi ◽

Moparthy Gurunadha Babu

Keyword(s):

Reversible Logic ◽

Content Addressable Memory ◽

Design And Implementation ◽

Ternary Content Addressable Memory

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Design and Implementation of an Improved GEP Algorithm for Synthesis of Reversible Logic Circuits

Proceedings of the 9th International Conference on Computer and Automation Engineering - ICCAE '17 ◽

10.1145/3057039.3057060 ◽

2017 ◽

Author(s):

Shuguang Zhao ◽

Chaozheng Wang ◽

Kaixiang Xia

Keyword(s):

Logic Circuits ◽

Reversible Logic ◽

Design And Implementation

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Speed and Power Efficient Reversible Logic Based Vedic Multiplier

2019 International Conference on Recent Advances in Energy-efficient Computing and Communication (ICRAECC) ◽

10.1109/icraecc43874.2019.8995165 ◽

2019 ◽

Author(s):

Ansiya Eshack ◽

S. Krishnakumar

Keyword(s):

Reversible Logic ◽

Power Efficient ◽

Vedic Multiplier

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An efficient design and implementation of Vedic multiplier in quantum-dot cellular automata

Telecommunication Systems ◽

10.1007/s11235-020-00669-7 ◽

2020 ◽

Vol 74 (4) ◽

pp. 487-496

Author(s):

B. Naresh Kumar Reddy ◽

B. Veena Vani ◽

G. Bhavya Lahari

Keyword(s):

Cellular Automata ◽

Quantum Dot ◽

Efficient Design ◽

Quantum Dot Cellular Automata ◽

Design And Implementation ◽

Vedic Multiplier

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Design and Implementation of High-Speed Low Power Multipliers Using Reversible Logic

INTERNATIONAL JOURNAL OF EMERGING TRENDS IN SCIENCE AND TECHNOLOGY ◽

10.18535/ijetst/v3i05.05 ◽

2016 ◽

Author(s):

Koustuv Chakraborty ◽

Keyword(s):

Low Power ◽

Reversible Logic ◽

Design And Implementation

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