Progress in VLSI Design and Test - Lecture Notes in Computer Science
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Published By Springer Berlin Heidelberg

9783642314933, 9783642314940

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Post-bond Stack Testing for 3D Stacked IC

Progress in VLSI Design and Test - Lecture Notes in Computer Science ◽

10.1007/978-3-642-31494-0_8 ◽

2012 ◽

pp. 59-68 ◽

Cited By ~ 1

Author(s):

Surajit Kumar Roy ◽

Dona Roy ◽

Chandan Giri ◽

Hafizur Rahaman

Keyword(s):

Stack Testing

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Design of Combinational and Sequential Circuits Using Novel Feedthrough Logic

Progress in VLSI Design and Test - Lecture Notes in Computer Science ◽

10.1007/978-3-642-31494-0_46 ◽

2012 ◽

pp. 367-369

Author(s):

Sauvagya Ranjan Sahoo ◽

Kamala Kanta Mahapatra

Keyword(s):

Sequential Circuits ◽

Combinational And Sequential Circuits

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Integrated Placement and Optimization Flow for Structured and Regular Logic

Progress in VLSI Design and Test - Lecture Notes in Computer Science ◽

10.1007/978-3-642-31494-0_41 ◽

2012 ◽

pp. 352-353

Author(s):

Vikram Singh Saun ◽

Suman Chatterjee ◽

Anand Arunachalam

Keyword(s):

Integrated Placement

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Power Modeling of Power Gated FSM and Its Low Power Realization by Simultaneous Partitioning and State Encoding Using Genetic Algorithm

Progress in VLSI Design and Test - Lecture Notes in Computer Science ◽

10.1007/978-3-642-31494-0_3 ◽

2012 ◽

pp. 19-29 ◽

Cited By ~ 3

Author(s):

Priyanka Choudhury ◽

Sambhu Nath Pradhan

Keyword(s):

Genetic Algorithm ◽

Low Power ◽

Power Modeling ◽

State Encoding

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Design of Push-Pull Dynamic Leaker Circuit for a Low Power Embedded Voltage Regulator

Progress in VLSI Design and Test - Lecture Notes in Computer Science ◽

10.1007/978-3-642-31494-0_2 ◽

2012 ◽

pp. 10-18

Author(s):

Biswajit Maity ◽

Pradip Mandal

Keyword(s):

Low Power ◽

Voltage Regulator

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An Efficient High Speed Implementation of Flexible Characteristic-2 Multipliers on FPGAs

Progress in VLSI Design and Test - Lecture Notes in Computer Science ◽

10.1007/978-3-642-31494-0_12 ◽

2012 ◽

pp. 99-110 ◽

Cited By ~ 1

Author(s):

Debapriya Basu Roy ◽

Debdeep Mukhopadhyay

Keyword(s):

High Speed ◽

Characteristic 2

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A Synthesis Method for Quaternary Quantum Logic Circuits

Progress in VLSI Design and Test - Lecture Notes in Computer Science ◽

10.1007/978-3-642-31494-0_31 ◽

2012 ◽

pp. 270-280 ◽

Cited By ~ 7

Author(s):

Sudhindu Bikash Mandal ◽

Amlan Chakrabarti ◽

Susmita Sur-Kolay

Keyword(s):

Quantum Logic ◽

Synthesis Method ◽

Logic Circuits

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Ultra-Low Power Sub-threshold SRAM Cell Design to Improve Read Static Noise Margin

Progress in VLSI Design and Test - Lecture Notes in Computer Science ◽

10.1007/978-3-642-31494-0_16 ◽

2012 ◽

pp. 139-146 ◽

Cited By ~ 7

Author(s):

Chandrabhan Kushwah ◽

Santosh K. Vishvakarma

Keyword(s):

Low Power ◽

Cell Design ◽

Static Noise Margin ◽

Ultra Low Power ◽

Noise Margin ◽

Sram Cell ◽

Static Noise

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Design of Content Addressable Memory Architecture Using Carbon Nanotube Field Effect Transistors

Progress in VLSI Design and Test - Lecture Notes in Computer Science ◽

10.1007/978-3-642-31494-0_27 ◽

2012 ◽

pp. 233-242 ◽

Cited By ~ 7

Author(s):

Debaprasad Das ◽

Avisek Sinha Roy ◽

Hafizur Rahaman

Keyword(s):

Carbon Nanotube ◽

Field Effect ◽

Field Effect Transistors ◽

Memory Architecture ◽

Content Addressable Memory

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Reusable and Scalable Verification Environment for Memory Controllers

Progress in VLSI Design and Test - Lecture Notes in Computer Science ◽

10.1007/978-3-642-31494-0_24 ◽

2012 ◽

pp. 209-216

Author(s):

Kiran Kumar Abburi ◽

Siva Subrahmanya Evani ◽

Sajeev Thomas ◽

Anup Aprem

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Progress in VLSI Design and Test - Lecture Notes in Computer ScienceLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By Springer Berlin Heidelberg

Post-bond Stack Testing for 3D Stacked IC

Design of Combinational and Sequential Circuits Using Novel Feedthrough Logic

Integrated Placement and Optimization Flow for Structured and Regular Logic

Power Modeling of Power Gated FSM and Its Low Power Realization by Simultaneous Partitioning and State Encoding Using Genetic Algorithm

Design of Push-Pull Dynamic Leaker Circuit for a Low Power Embedded Voltage Regulator

An Efficient High Speed Implementation of Flexible Characteristic-2 Multipliers on FPGAs

A Synthesis Method for Quaternary Quantum Logic Circuits

Ultra-Low Power Sub-threshold SRAM Cell Design to Improve Read Static Noise Margin

Design of Content Addressable Memory Architecture Using Carbon Nanotube Field Effect Transistors

Reusable and Scalable Verification Environment for Memory Controllers

Progress in VLSI Design and Test - Lecture Notes in Computer Science
Latest Publications